A method to implement sequence of events recording (SOE) based on FPGA
Introduction and overview
This is the first blog I’ve ever written, and it’s really about the functions of an application developed by myself at work.
As the name suggests, Sequence of Event (SOE) means that the system records changes in events at a certain moment, and is widely used in industrial control systems. In the field of industrial control, such as water conservancy plants, power plants, substations and other application scenarios, SOE event information requires millisecond-level high resolution to distinguish the sequence of state changes of each switch signal, which is mainly used when an accident occurs. Record the exact time of multiple switch input signal changes to help identify the cause of the accident in the event of an accident. It can be said that SOE is an important equipment for operating status monitoring, recording, and accident analysis in industrial control systems, and is a necessary function of industrial control systems.
This article will provide a method to implement the SOE event recording function based on FPGA. It uses GPS + Beidou timing equipment to synchronize time with the FPGA internal real-time clock, and uses the synchronized timestamp after time synchronization for event recording, which can achieve ms-level resolution. rate, and the trigger mode of event recording can be directly programmed and configured in the FPGA.
System Block Diagram
The GPS+Beidou timing system provides standard UTC time and PPS second pulse signals. The CPU module obtains the standard UTC time from the timing system and sends it to the FPGA module through the bus after format conversion. When the PPS second pulse arrives, the internal crystal oscillator in the FPGA The generated real-time clock is synchronized with the standard world time provided by the CPU to the FPGA, and the synchronized timestamp is used for event recording. The switch value is input from the outside, and the value (0 or 1) at that moment is recorded when the switch value changes. This data is called event record data. When the ARM is powered on, the changed event record data is read in real time and cached in Flash. When the ARM is powered off, the data is written into the FPGA's dual-port RAM cache. Finally, the CPU reads the data in the FPGA's dual-port RAM and uploads it to the host computer for display.
Time synchronization
The most important step of SOE is to synchronize the FPGA internal time with the standard world time. Only by accurately synchronizing the time can the changes that occur at a certain moment be accurately recorded. This function uses second time synchronization to synchronize the FPGA time when the PPS second pulse arrives. The specific method is as follows:
judge in the FPGA that if the time sent by the CPU differs from the real-time clock inside the FPGA by more than 1s, the time will be synchronized when the PPS second signal arrives. The two are synchronized.
The time adjustment method is to directly assign the seconds bit (that is, the high 32 bits) of the time issued by the CPU to the seconds bit of the FPGA internal real-time clock (that is, the high 32 bits), and clear the millisecond bit (that is, the low 32 bits) of the FPGA real-time clock to 0.
If the difference between the two times is within 1s, it switches to the FPGA internal real-time clock self-correction, that is, the second bit increases automatically.
(Explanation: Why should we judge whether the two times differ by 1 second? Because the PPS signal is a second time synchronization signal, it corresponds to the time below the second digit, so the behavior of cross-second time synchronization cannot always occur, otherwise it will cause the time after the time adjustment. The phenomenon of rollback.)
Verilog code design (for reference only)
`define SYS_CLK_PERIOD 32'd20
module sycn_time(
input wire clk,
input wire pps,
input wire rst,
input wire [63:0] cpu_time,
output reg [63:0] time_sync
);
assign time_sync = rtc;
reg [63:0] rtc;
reg pulse;
reg pulse1;
assign pulse1 = (rtc[31:0] >= (32'd100_000_000 - `SYS_CLK_PERIOD));
always @(posedge clk,posedge rst)begin
if(rst)begin
pulse <= 1'b0;
end
else
begin
if(pps)
begin
pulse <= 1'b0;
end
else if(((rtc[63:32] - cpu_time[63:32] > 1) && (rtc[63:32] > cpu_time[63:32])) || ((cpu_time[63:32] - rtc[63:32] > 1) && (cpu_time[63:32] > rtc[63:32] )) )
begin
pulse <= 1'b1;
end
else
begin
pulse <= pulse;
end
end
end
always @(posedge clk,posedge rst)begin
if(rst)begin
rtc <= 64'b0;
end
else
begin
if(pps && pulse)
begin
rtc[63:32] <= cpu_time[63:32];
rtc[31:0] <= 32'd0;
end
else if(pps || pulse)
begin
rtc[63:32] <= rtc[63:32] + 1'b1;
rtc[31:0] <= 32'd0;
end
else
begin
rtc[63:32] <= rtc[63:32];
rtc[31:0] <= rtc[31:0] + `SYS_CLK_PERIOD;
end
end
end
endmodule
Pulse change detection and mode switching (Verilog code design-for reference only)
module pulse_cmp(
input wire clk,
input wire DI,
input wire rst,
input wire Mode,
output reg trigger_pulse
);
reg DI_dly;
always @(posedge clk,posedge rst)begin
if(rst)begin
DI_dly<= 0;
end
else
begin
trigger_pulse <= 0;
DI_dly <= DI;
if(((Mode == 2'b00) || (Mode == 2'b11)) && (DI_dly != DI)) //双边沿触发模式
begin
trigger_pulse <= 1;
end
else if((Mode == 2'b01) && (DI_dly > DI)) //下降沿触发模式
begin
trigger_pulse <= 1;
end
else if((Mode == 2'b10) && (DI_dly < DI)) //上升沿触发模式
begin
trigger_pulse <= 1;
end
end
end
endmodule
This module is mainly designed to detect changes in the input switch value (DI value). The trigger_pulse signal is the trigger signal when DI changes. Mode can be input by the host computer to achieve controllable trigger mode.
Event record data caching and reading and writing
This module is relatively a core module, and it is not convenient to provide code here. Let me briefly talk about the design idea. In fact, it is to cache the recorded data into the dual-port RAM, and then perform read and write operations on the RAM. The read and write operations require corresponding read and write enable, read and write addresses. This design It is implemented by communicating with ARM to operate the register address. As can be seen from the previous block diagram, the data will be cached in ARM's Flash, then read by the CPU module, and finally uploaded to the host computer for display.
result
The final results after testing are as follows. The following is without time synchronization and in the rising edge trigger mode (only one DI input is given, because it is a rising edge trigger, so this data will only be recorded to high level 1) Get the recorded results.
In addition, it should be noted that the test pulse I gave is flipped once every 10ms (the period is 20ms), so this function can accurately record the time when the DI changes given by the user.
Finally, I will update my knowledge about FPGA from time to time and summarize the questions I encountered at work. Interested friends can communicate through private messages (only technical questions will be answered). The above is my personal technology at work. In conclusion, please correct me if there is anything wrong, and please do not reprint without permission.