Verilog——Simple and practical use of Chipscope (based on ISE14.7)
FPGA programming cannot avoid the need for online debugging. XILINX's ISE provides the Chipscope tool for online debugging.
But after checking many Chipscope debugging methods before, I always felt that many of these methods were complicated and lengthy. Recently I found a simpler online debugging method for Chipscope.
Two steps for Chipscope online debugging:
- Generate Chipscope files (generated files can be saved and reused later)
- Chipscope online debugging in the project
1. Generate Chipscope file
The four files generated in this step can be saved, copied directly in other projects in the future, and added to the project.
The final four files generated are:
- chipscope_ila.v
- chipscope_ila.ngc
- chipscope_icon.v
- chipscope_icon.ngc
2. Chipscope online debugging in the project
1) Code modification,
add the last four files generated in the previous step to the project to be debugged, and then infer which signals of which module (take the rd_req and rd_cmd signals as an example) based on the problems that occur in the program. Then add debugging code to the module in question:
//DEBUG
//---------------------------------------------------------------------
wire [ 35:0] CONTROL0 ;
wire [255:0] TRIG0 ;
chipscope_icon icon_debug(
.CONTROL0 (CONTROL0) //INOUT BUS[35:0]
);
chipscope_ila ila_filter_debug(
.CONTROL (CONTROL0 ),
.CLK (clk50M ),
.TRIG0 (TRIG0 )
);
//以上代码直接复制粘贴
//=====================================================================
//以下代码请根据自己的程序进行修改
//---------------------------------------------------------------------
assign TRIG0[0] = rd_req ;//待观测信号
assign TRIG0[4:1] = rd_cmd ;//待观测信号
After completing the code modification, recompile the project and connect to the emulator to download the program.
2) Start Chipscope
-
Click Xilinx Designer Tools -> Analyzer to start Chipscope
-
After starting, click the button below to connect to the circuit board
-
Click OK when the following dialog box pops up.
-
Enter the Chipscope main interface. The main interface of Chipscope mainly includes the project window, signal window, trigger condition setting serial port, and waveform window.
-
In the main interface, first set the signal of the waveform window. The main purpose is to combine and name each DataPort signal so that the signals output in the debug code correspond to the observation data interface. Right-click the signal and select Rename to rename:
Select multiple signals, right-click and select Move to Bus -> New Bus to combine the selected signals.
-
Then set the trigger conditions for the signal in the Trigger Setup trigger condition setting window. Find the trigger signal in the Match window under the Trigger Setup serial port and set the trigger condition Value. The trigger conditions include:
| symbol | Triggering conditions |
|---|---|
| X | Undefined value (default) |
| 0 | logic 0 |
| 1 | Logic 1 |
| R | rising edge |
| F | falling edge |
| N | non-edge |
- After completing the setting of trigger conditions, click "▶" to start debugging. When the set trigger conditions are encountered, the Waveform window will display the captured waveform, so that you can start observing the waveform to find bugs. If the trigger conditions are not modified, that is, all are X, the waveform window will display the waveform, but it may not be what you want.