Verilog and C language include header files similar to precompilation directives including the following:
- `define
- `include
- `ifdef
- `elsif
- `else
- `endif
It should be noted that the reference to the .vh file after the ` include directive must contain the absolute path of the file !
- 1) The following is an example of using precompiled directives. Set the flip time of simulation and actual code led0 through
ifdef ,
elsif, `endif .
module top(
input clk50M ,
input rst_n ,
output led0
);
//localparam
//=========================================================
`define TEST ;
`ifdef TEST //仿真程序代码
localparam TIME_1S = 50_000 ;//1ms
localparam TIME_500ms = 25_000 ;//0.5ms
`elsif TRUE //实际程序代码
localparam TIME_1S = 50_000_000 ;//1s
localparam TIME_500ms = 25_000_000 ;//0.5s
`endif
//=========================================================
reg [31:0] num;
//=========================================================
//num
//---------------------------------------------------------
always @(posedge clk50M or negedge rst_n) begin
if(~rst_n)
num <= 32'd0;
else if(num >= TIME_1S - 1)
num <= 32'd0;
else
num <= num + 1'b1;
end
//led0
assign led0 = (num >= TIME_500ms) ? 1'b1 : 1'b0;
endmodule
- 2) Below is another example of using precompiled directives.
- head.vh file code
//head.vh
//`define CAL_SUM
`define CAL_MINUS
- cal.v file code
//cal.v
`include "D:\\study\\modelsim\\acd_3_9_4\\src\\head.vh"
module cal(
input [7:0] ina ,
input [7:0] inb ,
output [15:0] out
);
`ifdef CAL_SUM
assign out = ina + inb;
`elsif CAL_MINUS
assign out = ina - inb;
`else
assign out = ina * inb;
`endif
endmodule