RMII interface overview
The RMII interface has 12 signal lines. All signal names are explained from the MAC layer side and mainly include four parts. The first is the sending data interface from the MAC layer to the physical layer, the second is the receiving data interface from the MAC layer to the physical layer, the third is the clock interface between the physical layer and the MAC layer, and the fourth is the data management between the MAC layer and the physical layer. MDIO/MDC interface.
Interface picture analysis
Pin definition analysis
TXD[1:0]: Data transmission signal line, the data bit width is 2, which is half of the MII interface.
RXD[1:0]: Data receiving signal line, the data bit width is 2, which is half of the MII interface.
TXEN (Transmit Enable): Data transmission enable signal, which has the same function as the signal line in the MII interface.
RXER (Receive Error): Data reception error prompt signal, which has the same function as the signal line in the MII interface.
CLKREF: It is a 50MHz reference clock provided by an external clock source. Unlike the MII interface, the receiving clock and transmitting clock in the MII interface are separated, and both are provided to the MAC chip by the PHY chip. It should be noted here that since the data receiving clock is provided by an external crystal oscillator rather than extracted from the carrier signal, a FIFO needs to be designed in the data receiving part of the PHY layer chip to coordinate two different clocks. Provides buffering for data. The sending part of the PHY layer chip does not require FIFO, it just sends the received data directly to the MAC.
CRSDV: This signal is composed of the two signals RX_DV and CRS in the MII interface. When the medium is not idle, CRS_DV and RECLK are given asynchronously. When CRS ends earlier than RXDV (that is, when the carrier disappears and there is still data in the queue to be transmitted), CRSDV will switch back and forth between 0 and 1 at the boundary of the nibble at a frequency of 25MHz/2.5MHz. Therefore, MAC can accurately recover RXDV and CRS from CRSDV.
At the 100Mbps rate, TX/RX samples one data per clock cycle; at the 10Mbps rate, TX/RX samples one data every 10 cycles, so the TX/RX data needs to be retained on the data line for 10 cycles, which is equivalent to One piece of data is sent 10 times.
When the PHY layer chip receives a valid carrier signal, the CRS_DV signal becomes valid. If there is no data in the FIFO at this time, it will send all 0 data to the MAC, and then when the FIFO is filled with a valid data frame, The beginning of the data frame is the "101010-" interleaved preamble. When the "01" bit appears in the data, it represents the start of formal data transmission. The MAC chip detects this change and starts receiving data.
When the external carrier signal disappears, CRSDV will become invalid, but if there is still data in the FIFO to be sent, CRSDV will become valid again in the next cycle, and then invalid and then valid until the data in the FIFO is sent. If an invalid carrier signal or invalid data encoding occurs during the reception process, RXER will become valid, indicating a physical layer chip reception error.
Connection method
MAC-to-PHY RMII connection
The RMII connection of MAC-to-PHY is relatively simple, just connect the corresponding signals directly.
