Article directory
- 1. VL1 output 1
- 2. VL2 wire connection
- 3. VL3 multi-wire connection
- 4. VL4 inverter
- 5. VL5 AND gate
- 6. VL6 NOR door
- 7. VL7 XOR gate
- 8. VL8 logic operation
- 10. VL10 logical operation 2
- 11. VL11 multi-bit signal
- 12. VL12 signal sequence adjustment
- 13. VL13 bit operations and logical operations
- 14. VL14 operates on signals bit by bit
- 15. VL15 signal level combination
- 16. VL16 signal inversion output
- 17. VL17 ternary operator
- 18. VL18 multi-bit signal xnor
- 19. VL19 five to one selector
- 20. VL20 256 select 1 selector
1. VL1 output 1
Description
Construct a circuit with no inputs and an output that outputs a constant 1. Input
Description:
None
Output Description:
The output signal is one.
`timescale 1ns/1ns
module top_module(
output one
);
assign one = 1;
endmodule
2. VL2 wire connection
Description
Creates a block with one input and one output that behaves like wires on a circuit.
Input description:
input signal in0
Output description:
output signal out1
`timescale 1ns/1ns
module wire0( input in0, output out1
);
assign out1 = in0;
endmodule
3. VL3 multi-wire connection
Description
Create a module with 2 inputs and 3 outputs, using wire connections:
a -> z
b -> x
b -> y
Input description:
input wire abOutput
description:
output wire xyz
`timescale 1ns/1ns
module top_module(
a, b, x, y, z
);
input a, b;
output x, y, z;
assign x = b;
assign y = b;
assign z = a;
endmodule
4. VL4 inverter
Description
Outputs the opposite value of the input signal.
Input description:
in
Output description:
out
`timescale 1ns/1ns
module top_module(
input in,
output out
);
assign out = ~in;
endmodule
5. VL5 AND gate
Description
Create a module that implements an AND gate. There are three wires as inputs, and the three signals (abc) are ANDed. Please think about how many AND gates are needed in the actual circuit? Please write the corresponding RTL
input description:
abc
output description:
d
`timescale 1ns/1ns
module top_module(
input a,
input b,
input c,
output d );
assign d = a & b & c;
endmodule
6. VL6 NOR door
Description
Create a module that implements OR and NOR. The NOR gate is an OR gate with an inverted output.
c is nor output, d is or output.
Input description:
ab
Output description:
cd
`timescale 1ns/1ns
module top_module(
input a,
input b,
output c,
output d);
assign c = a ~| b;
assign d = a | b;
endmodule
7. VL7 XOR gate
Description
Create a module that implements the XOR gate
Input description:
ab
Output description:
c
`timescale 1ns/1ns
module top_module(
input a,
input b,
output c );
assign c = a ^ b;
endmodule
8. VL8 logic operation
Description
Write the RTL logic as shown in the figure, limiting the use of up to four assign
input descriptions:
abcd
output description:
ef
`timescale 1ns/1ns
module top_module (
input a,
input b,
input c,
input d,
output e,
output f );
wire out_xor;
assign out_xor = (a & b) ^ (c | d);
assign e = ~out_xor;
assign f = out_xor;
endmodule
9. VL9 analog logic chip
Description
The following picture shows the logic of a certain chip. Please implement its function through RTL.
Input description:
p1a, p1b, p1c, p1d, p1e, p1f,p2a, p2b, p2c, p2d
Output description:
p1y, p2y
`timescale 1ns/1ns
module top_module (
input p1a, p1b, p1c, p1d, p1e, p1f,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y = (p1a & p1b & p1c) | (p1f & p1e & p1d);
assign p2y = (p2a & p2b) | (p2c & p2d);
endmodule
10. VL10 logical operation 2
Description
Based on the following logic, the corresponding module design is given.
Input description:
abcd
Output description:
ef
`timescale 1ns/1ns
module top_module (
input a,
input b,
input c,
input d,
output e,
output f );
wire out_xor;
assign out_xor = (a & b) ^ (c ^ d);
assign e = ~out_xor;
assign f = out_xor | d;
endmodule
11. VL11 multi-bit signal
Description
Construct a signal with a 3-bit input in [2:0], split it into three independent outputs abc (from 2 to 0) Input
description:
in
Output description:
abc
`timescale 1ns/1ns
module top_module(
in, a, b, c
);
input [2:0] in;
output a, b, c;
assign a = in[2];
assign b = in[1];
assign c = in[0];
endmodule
12. VL12 signal sequence adjustment
Description
A 16-bit signal in contains four four-digit numbers [3:0]a[3:0]b[3:0]c[3:0]d. Invert their order to dcba output and output out input description
:
in
output description:
out
`timescale 1ns/1ns
module top_module(
in, out
);
input [15:0] in;
output [15:0] out;
assign out = {
in[3:0], in[7:4], in[11:8], in[15:12] };
endmodule
13. VL13 bit operations and logical operations
Description
There is a module with input signals [2:0]a and [2:0]b. Please output the bitwise OR [2:0]c and OR signal d of the signal.
Input description:
[2:0]a [2:0]b
Output description:
[2:0]cd
`timescale 1ns/1ns
module top_module(
input [2:0] a,
input [2:0] b,
output [2:0] c,
output d
);
assign c = a | b;
assign d = a || b;
endmodule
14. VL14 operates on signals bit by bit
Description
Perform each bit of a five-input signal separately: All bitwise AND; All bitwise OR; All bitwise XOR
Input description:
[4:0]in
Output description:
out_and, out_or, out_xor
`timescale 1ns/1ns
module top_module(
input [4:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = & in;
assign out_or = | in;
assign out_xor = ^ in;
endmodule
15. VL15 signal level combination
Description:
Convert 6 input signals in series into four signal outputs. The input signals are [4:0] a[4:0] b[4:0]c [4:0]d [4:0]e [4: 0]f, add a 3 with a width of two bits at the end to form a 32-bit length, and output [7:0]w [7:0]x [7:0]y [7:0] in order from front to back. zInput
description:
[4:0] a[4:0] b[4:0]c [4:0]d [4:0]e [4:0]f Output description: [7:0]
w
[ 7:0]x [7:0]y [7:0]z
在`timescale 1ns/1ns
module top_module(
input [4:0] a, b, c, d, e, f,
output [7:0] w, x, y, z );
assign {
w, x, y, z } = {
a, b, c, d, e, f, 2'b11};
endmodule
16. VL16 signal inversion output
Description
Input a 16-bit signal in, and output it from low to high (that is, reverse the order output) as out
Input description:
[15:0] in
Output description:
[15:0] out
`timescale 1ns/1ns
module top_module(
input [15:0] in,
output [15:0] out
);
reg [15:0] out;
integer i;
always@(*)begin
for(i=0; i<=15; i=i+1) begin
out[15-i] = in[i];
end
end
endmodule
Personally, I have completed 90% of it. I always fail to use initial here at the beginning.
I need to figure out the usage of always and initial.
17. VL17 ternary operator
Description
Given four unsigned numbers, find the maximum value. Do not use if for judgment, and use as few statements as possible to complete it.
Input description:
[7:0]abcd
Output description:
[7:0] max
`timescale 1ns/1ns
module top_module(
input [7:0] a, b, c, d,
output [7:0] max);
assign max = (((a >= b) ? a:b)>=((c>=d)? c:d)) ?((a >= b) ? a:b):((c>=d) ? c:d);
endmodule
Note: I did separate comparison tests at first but didn't use them. In the end, I just did it in one line. Since I used as few statements as possible, I just did it in one line.
18. VL18 multi-bit signal xnor
Description:
Given five 1-bit signals (a, b, c, d and e), two types of 25-bit data are generated: one is to copy the signal five times and then connect it aaaaabbbbb..., and the other is to connect the signal and copy it five times. Times become abcdeabcde… . Compare two 25-bit signals. If the bits at the same position of the two signals are equal, 1 is output.
Input description:
a, b, c, d, e,
output description:
[24:0] out
`timescale 1ns/1ns
module top_module(
input a, b, c, d, e,
output [24:0] out
);
assign out = {
{
5{
a}}, {
5{
b}}, {
5{
c}}, {
5{
d}}, {
5{
e}}} ~^ {
5{
a, b, c, d, e}};
endmodule
19. VL19 five to one selector
Description
Input five 4-bit signals and select the corresponding signal according to the value of sel. The corresponding relationship is: 0~a 1~b 2~c 3~d 4~e Others~set to zero. Input description: [3:0
]
abcde
[ 2:0] sel
output description:
[3:0] out
`timescale 1ns/1ns
module top_module(
input [3:0] a, b, c, d, e,
input [2:0] sel,
output reg [3:0] out );
always @(*)
case(sel)
3'b000: out = a;
3'b001: out = b;
3'b010: out = c;
3'b011: out = d;
3'b100: out = e;
default: out =0;
endcase
endmodule
20. VL20 256 select 1 selector
Description
Input a 256-bit signal, and output the corresponding bit value according to the sel signal. When sel = 0, select in[0], when sel = 1, select in[1], and so on. Input description: [255:0]
in
[
7 :0]sel
output description:
out
`timescale 1ns/1ns
module top_module (
input [255:0] in,
input [7:0] sel,
output out
);
assign out = in[sel];
endmodule
At the beginning of this question, I have been struggling with what to do if the index is binary and not a constant. I wanted to use a for loop, but I was stuck on the index. I looked at someone who assigned the value directly, and it actually worked.