1. Abnormal reset problem of STM32’s NRST pin
This problem occurred when the customer did the EMS surge test on the developed platform, and a STM32G474 RCT6 MCU was used on the platform. During a certain level of EMS testing, the customer found that the MCU sometimes resets abnormally, which affects the stable operation of the platform.
Common solutions to MCU abnormal reset problems:
We know that there are many reasons for the MCU to reset abnormally, such as interference with the external reset circuit, abnormal drop of the MCU power supply, reset caused by the watchdog not being able to feed the dog normally, etc.
The reset flag register of the STM32 MCU can help us find clues that cause abnormal resets.
Information about reset flags can be found in the Reference Manual of the STM32 MCU. In the RCC_CSR register in the RCC section, we can see that 
the part surrounded by red in the figure is the register related to the reset flag.
LPWRRSTF: Low-power mode reset flag bit, if it is set to 1, it means that an illegal STOP, SLEEP or SHUTDOWN low-power mode entry has occurred.
WWDGRSTF: Window watchdog reset flag.
IWDGRSTF: independent watchdog reset flag.
SFTRWTF: Software reset flag.
BORRSTF: Brown-out reset flag.
PINRSTF: Flag bit for reset generated from NRST pin input.
OBLRSTF: Flag bit for reset generated by loading option byte.
The above flag bits are set to 1 to indicate that the associated reset has occurred.
These set flag bits can be cleared by writing 1 to the RMVF bit.
During a normal MCU power-on process, the rise in voltage and the operation of the PDR circuit will inevitably cause BORRSTF and PINRSTF to be set to 1. Therefore, before doing the EMS experiment, you need to clear all reset flags by writing 1 to RMVF. Then observe which reset flags are set after the reset caused by the EMS test.
For example, when observing that BORRSTF is set to 1 indicates that an undervoltage reset has occurred, it is necessary to focus on checking the MCU power supply circuit including the design and layout of the filter/decoupling capacitor, etc.
The PINRSTF bit is set to 1 to indicate that the NRST pin of the MCU has received an abnormal low level that can trigger a reset. You need to check how the peripheral circuit of the NRST is interfered, or try to add a filter circuit to filter out the interference.
WWDGRSTF or IWDGRSTF is set to 1, indicating that the dog feeding is abnormal and causes a reset. This is generally caused by the program running abnormally and entering an endless loop during the EMS test. The way in which the MCU is affected by EMS interference is relatively difficult to determine. It may be the ground or some/some The GPIO pins are invaded by EMS interference and affect the normal operation of the MCU.
By observing the reset flag bit after an abnormal reset occurs, we can avoid wasting time on irrelevant circuits when solving problems. For example, if only BORRSTF is set, we need to focus on the power supply circuit and do not need to worry about the reset pin. The circuit makes useless adjustments.
Troubleshooting on the customer development platform:
Based on the idea described above, we investigated the cause of the abnormal reset on the customer's platform. By checking the reset flag bit of STM32G4, we found that PINRSTF was set to 1 after the reset occurred.
This seems to be a simple NRST reset pin being disturbed.
But observing the customer's design, the NRST pin is not connected to an external circuit with a relatively long trace, but a 0.1UF capacitor is placed on the pin. Normally such a circuit will not introduce interference into the NRST pin. 
In order to prevent the 0.1UF capacitor from introducing ground noise into the pin, the surge test was performed after removing this capacitor, and the result is that PINRSTF is still set.
STM32G4 has a new feature. The NRST pin can be reused as a GPIO PG10. When this pin is defined as PG10, low-level interference added to this pin will no longer cause the MCU to reset. But something strange happened. After pin 7 of STM32G474 was redefined from NRST to PG10 (modified in Option byte), PINRSTF was still set during the surge experiment.
At this time, it seems that the detection cannot be limited to the NRST pin. Is interference flowing into the MCU from other GPIOs and further affecting the work of the reset circuit through coupling?
In the LQFP package, due to the existence of long parallel bonding lines inside the MCU, coupling interference is most likely to occur between adjacent GPIOs, so we start troubleshooting from pins 6 and 8 adjacent to pin 7. Disconnect their external signals respectively. Through investigation, the disconnection of the 8th pin signal did not solve the problem. whaosoft aiot http://143ai.com
But when the crystal oscillator and capacitor connected to pin 6 are disconnected, and the internal HSI clock source is used instead, the abnormal reset problem disappears, and PINRSTF is no longer set. It seems that the interference comes from the 7th foot. Observing the customer's PCB design, we found that the grounding of the LOAD capacitor of the crystal oscillator is not directly connected to the ground plane, but is connected to the ground plane through a slender ground trace through a via hole. It is obvious that this slender ground trace is connected to the ground plane. In the surge test, it acts as an antenna to receive interference and transmits it to the inside of the MCU through the capacitor.
Summarize
The interior of the MCU is a microelectronic circuit that is far more complex than the external circuit of the MCU. The internal circuit spacing is small, and different functions may only be selected by electronic switches or multiplexers. When high-frequency interference enters the MCU, the interference can appear to Coupling between circuits that are not directly connected affects the normal operation of the MCU.
It is important to avoid interference entering the MCU. When troubleshooting the path of interference transfer, don't limit your eyes to directly connected circuits or pins.