We all know that the IO of FPGA is divided into multiple BANKs. At first, I thought that the purpose of this design was only to meet the needs of FPGA to interact with peripherals of different levels. Later, I found out that I was superficial. Different BANKs can be used not only to adapt to different level standards, but also to adapt to different rate requirements. For example, in video streaming, with the development of technology, the resolution of video has also increased. A few years ago, 1080P was regarded as the industry benchmark, but now it cannot support 4K and 8K. Like traditional video interfaces mipi, openLDI, cameraLink, etc., these are all conventional LVDS level standards (no Serdes dedicated interface is required).
Taking 1920x1080@60Hz as an example, the pixel clock is about 150Mhz (1920x1080x60x1.2, where 1.2 is the loss estimate of the front and back of the video), and the transmission frequency of the IO port after serial conversion is about 1050Mbps (calculated according to RGB888, 4lane transmission) , performance and wide voltage range are often not both. In order to obtain higher transmission performance, a certain voltage input range must be sacrificed, so Xilinx divides BANK into two types (actually three types, ultrascale devices There is also HD BANK in):
HP BANK: High Performance High Performance
HR BANK : High Range High voltage range.
The figure below is the BANK distribution diagram of the 7K325T device
Image source UG471
Briefly describe the difference between HR BANK and HP BANK
1. Support of underlying components
Image source UG471
From the above table, we can find that HR BANK does not support ODELAY, and HP BANK does not support ZHOLD_DELAY; as for what is ODELAY and what is ZHOLD_DELAY, we will talk about the underlying structure later, so we won’t go into details for now.
2. Supported level standards
Image source UG471
HRbank can support a wider voltage range than HP BANK, basically from 1.2V~3.3V single-ended voltage standard
Both are supported, but HP BANK supports DCI and Vccaux_io supply rail, both of which are related to DDR drivers,
If DDR is used in the design, it is recommended to connect DDR to HP BANK, why is it just a suggestion? Because HR BANK also
DDR can be driven, but the performance will be much worse.
DS182
Another point that needs special attention is: Although both HR BANK and HP BANK can support LVDS signals, HR BANK can only support LVDS_25, that is, the common-mode voltage is 2.5V; HP BANK can only support LVDS, and the common-mode voltage is 1.8V . I remember when using HR BANK to drive LVDS for the first time, I thought that HR BANK supports all levels of 1.2~3.3V, which is also effective for LVDS signals. The voltage of BANK is designed to be 1.8V. The result is various debugging. After finding the problem, various cutting The board flying line, the pit I stepped on, I hope people will not step on it later.
The LVDS I/O standard is only available in the HP I/O banks. It requires a V CCO to be
powered at 1.8V for outputs and for inputs when the optional internal differential
termination is implemented (DIFF_TERM = TRUE).
The LVDS_25 I/O standard is only available in the HR I/O banks. It requires a V CCO to be
powered at 2.5V for outputs and for inputs when the optional internal differential
termination is implemented (DIFF_TERM = TRUE).
Image source UG471
3. Supported speed
DS182
In SDR (single-edge sampling) mode, there is no difference between the maximum rate of HP BANK and HR BANK, but in DDR (double-edge sampling) mode, the rate of HP BANK is significantly improved compared to HR BANK.