I. Overview
- In the SV module, the overall construction of the verification environment is from the verification components of the underlying module to the communication and stimulus generation.
- Whether these elements are the creation, access, modification, configuration of software objects, or the communication between components, etc., they are all implemented in a user-defined way .
- The UVM verification methodology is to specify the reusable and standardized parts of the verification process in its methodology class library .
- Requirements for the verification environment: creation and access of components, creation of the structure of the environment, connection and operation of components, sequence arrangement of different phases, generation, delivery and control of stimuli, and reporting mechanisms for tests.
Two, UVM core class library
- Since the generation of objects in the software environment is dynamic, the components in the verification environment also need the underlying functions provided by UVM to complete the creation and access of objects.
- In addition to component creation, UVM also needs to provide sequential control methods for creating, connecting, and running components in the upper and lower levels of the environment. Only when this is effectively guaranteed on the underlying mechanism can the possible handle dangling problem be avoided.
- In component communication, UVM also provides a more functional TLM (Transaction level model) interface, which can ensure that the communication between adjacent components is no longer referenced by explicit handles, but is independent of the communication method of components.
- The generation and transmission of the test sequence (sequence) is also completed between the sequence and the driver by using the TLM transmission. For the transmission sequence control of different sequences, it is necessary to implement flexible scheduling between sequences.
- In order to facilitate the debugging of the verification environment, UVM's reporting mechanism can filter information from different components and levels, and finally generate a test report.
①Core base class : Provides the lowest-level support, including some basic methods such as copy, create, compare, and print.
②Factory (factory) class : Provides methods for registering environment components, creating components and overriding component types.
③ transaction (transaction) and sequence (sequence) class : used to specify the data type and data generation method in the TLM transmission pipeline.
④Structure creation (struct creation) class : constitutes the main part of the verification structure.
⑤Environment component (environment component) class : constitutes the main part of the verification structure, and the nesting relationship between components forms a structural hierarchical relationship through layer-by-layer instantiation and connection.
⑥ Communication channel (channel) class : together with the transaction interface class, it realizes the communication and storage between components.
⑦Message report class : It makes the information reported from the UVM environment consistent and standardized, which is convenient for overall control and filtering.
⑧Register model (register model) class : used to complete the modeling, access, and verification of registers and storage.
⑨Thread synchronization (thread synchronization) : more convenient than the SV synchronization method, and more information can be transmitted when synchronization occurs.
⑩Transaction interface (transaction interface) class : together with the pipeline communication class, it realizes the communication and storage between components.