foreword
The system design and simulation implementation of the two-way interleaved CCM totem pole was introduced earlier, and the simulation is ideal.
Then it introduces the principle of SOG phase-locked loop simulation implementation
Recently, the hardware has been ready, the model generation code has also been integrated, and it is being tested on the machine. Here are some test results, and more optimization work needs to be done in the future.
actual hardware test
Start the simulation:
The following figure is the start-up simulation, through the operation of the relay, the charging of the bus capacitor is realized
Yellow is the given Bus voltage, blue is the feedback voltage
The actual running effect on the hardware:
Output the change of the actual bus voltage and print it out through the host computer.
Simulate voltage and current waveforms:
Yellow is single-phase AC AC voltage, blue is current
Generate code for actual hardware running voltage and current waveforms:
Yellow is the sampled grid voltage, red is the sampled inductor current
At this point, the basic functions of the hardware have been realized, but in fact, there is still a lot of work that needs to be optimized.
performance optimization
The loop bandwidth is optimized. If the current loop control bandwidth is too small, the current may not be sinusoidal. The following is the waveform at low bandwidth. The current is asymmetrical and can be controlled, but the THD and PF are poor.
After increasing the current loop control bandwidth, the phases are basically synchronized, PF=0.997, THD<5%, and the performance can meet the national standard, but there is still room for improvement
notch filter
Simulation effect, there is 100Hz ripple before the blue filter, and almost a straight line after the yellow filter
The bus voltage sampled by the actual hardware is purple, and the red is the voltage after the notch filter. If it is directly sent to the voltage loop without filtering, it will cause the output of the voltage loop to oscillate, resulting in poor THD data and even system oscillation.
Optimizing THD also needs to optimize the peak current at the zero-crossing moment, as well as the current phase. As shown in the figure below, the soft start at the zero-crossing moment can avoid the peak current caused by the reverse recovery of the diode. The simulation has been completed, and the actual test of the generated code can also be normal. Avoid the generation of peak current. But it can be seen that the voltage and current do not coincide completely, and there is a little phase difference. At this time, it is necessary to compensate the current to avoid the current phase leading and reduce THD.
Summarize
From the beginning of modeling to the actual hardware operation, the entire process has been completed, and there are still many optimization tasks that need to be completed step by step. I will record it when I have time.