The memory is an important part of the microcontroller. Different types of microcontrollers have different storage structures and capacities, but the memory has the same purpose for storing programs and data. There are two basic forms of memory structures in microcontrollers.
von Neumann structure
Von Neumann structure, also known as Princeton structure, is a memory structure that combines program memory and data memory in the same addressing space. ROM and RAM point to different locations of the same memory, and the width of instructions and data is the same. It is a common A common storage structure for microcomputers.
The central processors using the von Neumann structure include: Intel's 8086 and its series processors, ARM's ARM7, and MIPS' MIPS processors.
harvard structure
The Harvard structure is an improvement and perfection of the von Neumann structure. It is a memory structure that divides program storage and data storage into two addressing spaces. The program and data are stored separately, allowing instructions and data to have different data widths. , is a commonly used data structure for microcontrollers. It has high execution efficiency.
Microcontrollers using the Harvard structure include: Microchip's PIC series chips, Motorola's MC68 series, Atmel's AVR series, and ARM's ARM9, ARM10 and ARM11, 8051 microcontrollers also belong to the Harvard structure.
Von Neumann Structure and Harvard Structure Summary
First of all, the most essential thing to distinguish between the two is to look at the memory. If the data memory and the program memory are separated, it is a Harvard structure, and vice versa, it is a von Neumann structure. Because there is only one memory, and the width of the contents stored in the same memory must be the same, the program instructions and data of the von Neumann structure have the same width. The Harvard structure has two memories, and the widths of different memories can be different, so instructions and data in the Harvard structure have different data widths.
In terms of execution efficiency, the execution efficiency of the Harvard structure is higher than that of the von Neumann structure. Von Neumann structure instructions and data share a bus, which means that when executing commands, the Von Neumann structure must first read instructions through the bus, and then operate on the data according to the instructions after reading. Every operation is the instruction first and then the data, and it is not possible to fetch instructions and operate data at the same time. The Harvard structure is different. Its two memories are separated, and there are two buses, which can operate on data when reading instructions. The two are performed at the same time, so the efficiency is higher.
Von Neumann structure: 1. Program memory and data memory are the same memory 2. Instruction and data width are the same
Harvard structure: 1. Program memory and data memory are separated 2. Instruction and data width are different 3. Execution efficiency is higher
STM32 system structure
The STM32F103 microcontroller is internally connected to each other through a multi-level AHB (advanced high-speed bus), as shown in the figure
Cortex-M3 adopts Harvard structure, so STM32 provides an independent instruction bus (ICode) for program instructions to connect to flash memory. Among them, FLITE is used to support instruction pre-storage, and has functions such as the read interface of the pre-fetch buffer, Flash programming and erasing operations, and read and write protection operations.
Both the Cortex core and the DMA unit can be used as bus masters. When they access the SRAM and peripheral bus at the same time, they need to use the president device to arbitrate the device using the bus. The bus matrix is used to arbitrate the processor core and DMA access, and is connected to 4 main buses: DCode, System (S-bus), and two DMA buses.
The bus matrix also connects 4 slave buses for connecting internal SRAM, internal flash memory (FLITE), variable static memory controller (FSMC, for connecting external memory) and AHB-APB conversion bridge. The AHB-APB conversion bridge connects all peripherals through two advanced peripheral buses APB. APB2 can work at full speed at 72MHz, but APB1 is limited to 36MHz, and the clock management of the entire system is realized through the RCC module.
Simply remember that the STM32 system structure consists of a bus matrix and its parts connected by the bus. Including 4 main buses and 4 slave buses, among the 4 main buses, DCode and System (S-bus) are connected to the Cortex-M3 core, and two DMA buses are connected to DAM1 and DMA2; 4 slave buses are respectively connected to internal SRAM and internal flash memory , external memory and AHB conversion bridge. The AHB conversion bridge connects the peripherals through APB1 and APB2.