Sequence Diagram Basics

For some timing diagrams that often appear in the reference manual, it often makes me puzzled. For example, for the timing diagram of Flash, if you want to understand it, you have to learn every parameter in it systematically, and some symbols in the timing diagram do not understand what they mean. When adjusting HyperRAM some time ago, because I didn’t understand those parameters, I couldn’t use an oscilloscope to analyze the waveform, and I didn’t know where to change the software, so I ended up trying to adjust it randomly. This article takes the 74HC595 chip as an example to introduce some basic concepts of timing diagrams.

1 Common Timing Diagram Symbols

First, let’s look at some common timings that are often encountered in timing diagrams. It should be noted that there is no unified standard for timing diagrams, so the timings listed below may be slightly different in different manuals, but these timings are all is very typical.
(1) Square wave

(2) Rising/falling edge : the arrow indicates that the signal is triggered

(3) Ramping (Ramping)
usually indicates a continuously changing signal whose value gradually increases or decreases over time. It is used to indicate a gradual change or transition of an analog signal, or to clearly indicate that two signals are opposite.

(4) White cross

This signal is a horizontal cross in the above picture. It indicates that the value of the corresponding signal can be a high value or a low value during the clock cycle in which it is sampled, its value is determined by an external event, and the data is sampled on the rising or falling edge.

(5) Gray cross
In the timing diagram, there can be several definitions related to the gray part, indicating that the chip does not care about the value. For example, I2C transmits 8 bits at a time, but only uses 3 bits of MSB, so the first 3 bits are white crosses, and the remaining 5 bits are gray crosses. There is another situation, that is, it can also be expressed in the high-impedance state. Refer to the timing of the 74HC595 below.

(6) Omit
The small gaps in the timing diagram below indicate that a large amount of data is being transmitted, so the timing diagram of each byte is not displayed here, but omitted. For example, Flash can transmit 256 bytes at a time, so it is impossible to show you the timing of 256 bytes in one sequence.

(7) Bit mark
The bit mark provides detailed data flow instructions, such as the 256 bytes just mentioned, here shows each byte in the timing diagram.

(8) Arrow : Two points that are not aligned in time, if connected by a one-way arrow (usually curved), it means that the generation of the previous sequence will lead to the generation of the subsequent sequence. For example, a rising edge of an external interrupt will cause the timing of the interrupt flag to change from low to high after several instruction cycles, and there will be an arrow pointing from the rising edge of the external interrupt to the rising edge of the interrupt flag in the timing diagram.

2 74HC595

2.1 74HC595 package

Here we take the 74HC595 chip as an example to introduce the related concepts of the timing diagram. 74HC595 is an 8-bit serial input, parallel output shift register. The package is as follows:

• Q _A ~ Q _H : Parallel data output
• SER: serial data input
• Q _H' : serial data output terminal
• RCLK: output memory latch clock line
• SRCLK: data input clock line
• $\overline{\text{SRCLR}}$: Reset, high level clears the output register
• $\overline{\text{OE}}$: output enable, active low

2.2 Timing diagram

DataFirst of all, let’s take a look at the situation where the input data line ( SER) is 0 when the clock pulse signal comes :

you can see that the latch signal is generated after the clock signal, and Datait is always 0. It seems that nothing is done here, so we continue To extend this timing diagram, pull DataHIGH.

We can see that in the next period of timing, CLOCKthe rising edge of , Datais a high level. Then after CLOCKthe sum Datais output, the latch signal changes the output QA.

Since this is a shift chip, let's add QB Outit to the timing now to see:

in the next clock cycle, another 0 is input, so after the latch, QAthe output of is shifted to QB, and QAthis time is saved 0.

Then we make up the remaining output pins, and Dataall the subsequent clock cycles output 0:
you can see that the 1 input in the first clock cycle is shifted one by one QH.

Now that we briefly know how the timing diagram works, let's take a look at the timing diagram in the real manual, the following is the timing diagram given in TI's SNx4HC595 manual: The timing diagram of all pins is listed in the figure,

where Q The dotted line at the beginning of _A ~Q _H indicates that the current output is unknown, because at this time $\overline{\text{SRCLR}}$When it is low, we don't know the previous state, and when it is pulled high, the data inside the register will be cleared and the output pin will be restored to the default state. Finally, there is a mesh timing, which means that the output is not enabled, that is, $\overline{\text{OE}}$When 1, the output goes to the third state of high impedance.

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As mentioned earlier, there is no standard for timing diagrams, so for 74HC595, the timing diagrams of 74HC595 produced by different manufacturers are a little different. Let’s take a look at the timing diagram of DIODE’s 74HC595 to analyze the data establishment time

: The part marked by the red box indicates that the data is sampled at the rising edge of the clock, and the DS should be kept stable at this time. The period of time in the red box (from the falling edge to the rising edge of the clock) is called the setup time. At the back of the manual, there is a detailed timing sequence of the data setup and hold:

where t _{su is the data setup time, which means that you need to ensure that the data on the data line is at least stable t su} before the clock signal comes . At the same time, after the clock becomes high level, the data should be kept at least t _h , so that the latch can normally save the data. Take the establishment time t _su as an example. If we do not meet this time requirement, the data may be abnormal. Now we need to look at the requirements of t _su in the manual : look at the line ( )

here , when VCC is 4.5V, temperature In the case of 25°C, the typical value of the data settling time is 4, it is just a representative value, in fact we should not set it lower than the minimum value of 10.DS to SHCPData set to SHCP

3 summary

This article briefly introduces the basics of timing diagrams, but if we open a timing diagram in a chip manual now, we will find that we still can’t read it, because it is actually much more complicated than these, we need to understand each sequence diagram in the manual. The meaning of a timing parameter, and then analyze the timing diagram.