filter design
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EMI Filter Design (Automotive Electronics)
1. Standard requirements
Take automotive electronics as an example:
The design form and topology of the EMI filter circuit for low-voltage DC power ports (such as 12VDC for passenger cars and 24VDC for commercial vehicles) are usually determined by the original noise of the internal power circuit & the test standard level. Taking the automotive electronics standard CISPR25 as an example, there are 5 levels of power port conduction tests: CLASS5, CLASS4, CLASS3, CLASS2, and CLASS 1; among them, CLASS 5 has the lowest limit line. When the original noise of the power circuit is constant, the insertion loss of the EMI filter circuit is required. The largest, the original noise of the power circuit is strongly related to the schematic design (power topology, absorption circuit, drive circuit, power device, filter device), PCB design (layout and wiring, layer assignment, moving point area, loop area), structure & cable design (shielding, grounding, isolation, wiring).
When the power circuit interference noise & test standard limits are determined, the filter circuit can be designed.
2. Design theory
2.1 Filter circuit design process
The EMI filter design of the power port is directly related to the EMI noise of the power port of the product and the limit value requirements of the test standard; before the product is formed, the filter circuit design is more based on historical experience design, such as: the practice of TOP competitors in the industry with the same product and the same port (ie: "Product EMC Analysis of Friends"), and the previous version of the same product with the same power circuit topology and the same port (ie: "Product EMC Design Experience Summary").
For true EMI filter design, after the product is formed, remove all filter components (X capacitors, Y capacitors, and common mode inductors) at the power port, test the original EMI noise of the power port (ie: naked noise), separate the original noise from differential common mode, and determine the differential common mode original noise. According to the test standard limit line, consider the 6dB margin to determine the differential common mode insertion loss of the filter circuit. Determine the Y capacitor value according to the frequency spectrum characteristics of the switching frequency, and determine the common-mode inductance through the common-mode interference corner frequency.
The differential mode component of conventional common mode inductors is about 0.5-1% of the common mode inductance, and the differential mode leakage inductance of the common mode inductor can be calculated and determined according to 0.5%, and the X capacitance can be determined by the differential mode interference corner frequency, and finally the filter circuit parameters can be determined.
2.2 Definition of insertion loss
In the filter circuit design, the insertion loss is usually used to reflect the loss and attenuation of the signal power before and after the filter circuit is used. The greater the insertion loss, the more attenuation and the better the filtering effect.
2.3 Raw noise measurement
Remove all the EMI filter circuits of the product and measure the original noise, but be aware that the high original EMI noise may exceed the range of the receiver. You can add X capacitors (such as: 1uF) and Y capacitors (such as: 1nF) to the port and finally compensate in the final filter circuit.
2.4 Calculation of insertion loss
Comparing the original differential mode noise and common mode noise with the standard test limit line, considering the 6dB margin, you can get the key frequency point (generally the first frequency point with the most excessive low frequency band, if there are two or more, you should follow the filter insertion loss characteristics, such as: a first-stage filter, composed of CLC, should be converted according to 60dB/decade, and determine which low frequency band exceeds the standard point as the key frequency point) Differential mode insertion loss and common mode insertion loss.
2.5 Principle of filter mismatch
In order to ensure the maximum insertion loss of the filter circuit, the topology of the filter circuit must follow the principle of mismatch; when the source impedance or load impedance is high impedance, matching capacitor filtering is required; when the source impedance or load impedance is low impedance, matching inductor filtering is required. The power supply EMI filter selection form is as follows:
High resistance and low resistance are relative. Differential mode loop LISN sampling resistor 50R is connected in series to be 100R; common mode loop LISN sampling resistor 50R is connected in parallel to be 25R; assuming differential mode interference frequency is 150kHz, 1uF X capacitor filtering is required, and the capacitance impedance is 1.1R; assuming common mode interference frequency is 10MHz, 103Y capacitor filtering is required, and the capacitance impedance is 1.6R; load impedance differential mode 100R/common mode 25R is relative to X capacitor 11R/Y Capacitors 1.6R are all high-impedance and specific to the power supply EMI filter circuit design. Due to the presence of PFC inductors in the BOOST circuit, it is assumed that the differential mode interference frequency is 150kHz, the PFC inductance is 100uH, and the inductance impedance is 94.2R (high resistance), so the filter circuit device near the PFC side is a capacitor; the BUCK circuit has capacitors. Assuming that the differential mode interference frequency is 150kHz, the differential mode capacitor is 10uF, and the capacitive impedance is 0.1R (low resistance), it is close to BUCK. The filter circuit device on the circuit side should be an inductor.
2.6 Filter topology selection
The load impedance is 100Q/25R (high impedance), so the first stage near the LISN side should have X capacitors and Y capacitors; the source impedance is uncertain, the power topology is different, and the source impedance is different; for example: BOOST circuit, with PFC inductor (high impedance); BUCK circuit, with X capacitor (low impedance); There should be a common-mode inductor on the side (the differential-mode inductor is realized by the differential-mode component of the common-mode inductor). The common EMI filter at the filter power port has one-stage filtering and two-stage filtering. The EMI filter circuit is as follows:
If the first-stage EMI filter circuit structure is adopted, the equivalent common-mode filter circuit structure is CLC, that is, the common-mode insertion loss curve attenuation is 60dB/+octave, and the equivalent differential-mode filter circuit structure is CLC, that is, the differential-mode insertion curve attenuation is 60dB/decade.
If a two-stage EMI filter circuit structure is adopted, the equivalent common-mode filter circuit structure is CLCLC, that is, the attenuation of the mode insertion loss curve is 100dB/+octave, and the equivalent differential-mode filter circuit structure is CLCLC, that is, the attenuation of the differential-mode insertion curve is 100dB/decade.
2.7 Calculation of filtering parameters
The insertion loss transfer function of the first-stage differential mode EMI filter and its amplitude-frequency characteristics, the minimum frequency point fTdm of differential mode noise , as shown in the figure below:
The insertion loss at the minimum frequency of differential mode noise is:
The corner frequency of the first stage differential mode EMI filter is fcdm:
The insertion loss transfer function of the two-stage differential mode EMI filter and its amplitude-frequency characteristics, the minimum frequency fTdm of the differential mode noise
is as follows:
The insertion loss at the minimum frequency of differential mode noise is:
The corner frequency fcdm of the two-stage differential mode EMI filter is:
If the filter circuit adopts two-stage filtering, Ldm1=Ldm=6.5uH, the differential mode inductance of conventional common mode inductors is about 0.5% of the common mode inductance , namely:
In general, the common mode inductance of manganese zinc material is difficult to achieve 15.7mH, unless the current is very small (1A and below), the common mode inductor winding is thin enough, the number of winding turns is enough, and the initial magnetic permeability of the magnetic core (zinc or amorphous) is high enough. For conventional common mode inductors, it is more common to achieve 6mH for small currents (3A and below), 2mH for medium currents (about 16A), and 0.8mH for large currents (32A and above). If the circuit is designed with a first-stage filter, it is very difficult to design and select a common mode inductor. If the circuit is designed with a two-stage filter, the common-mode inductance requires 1.3mH, which is very easy to implement, so a two-stage filter circuit design is used.
Assuming Y1 C=1nF, Y2, Y3=C=4.7nF, the common mode corner frequency of the two-stage filter is:
The common mode corner frequency of the primary filter is:
2.8 Determination of filtering parameters
通过计算两级滤波转折频率为107kHz，传导测试起始频率为150kHz，共模干扰频段一般在中频段(0.5-5MHz)和高频段(5-30MH)，按照100dB/十倍频程计算，1.07MHz频点即有100dB插损，共模滤波电路插入损耗足够，最终两级滤波电路设计为:Y电容(1022)-X电容(1uF)-共模电感(13mH)-Y电容(4722) -X电容(1uF)-共模电感 (1.3mH)-Y电容(472*2)-X电容(1uF)滤波电路如下图：
As above, the design and calculation process of the power port filter circuit is explained in detail. Except for the differences in test standards, test methods, limit value requirements, and product forms, the design and calculation process of the power port filter circuit for all products is essentially the same. The above design and calculation process is for analogy reference.