GVIM-verilog common code

1. Design code

1 Combinational logic for always

always@(*)begin
end

2 sequential logic

• sync rst

always@(posedge clk)begin
	if(!rst)

	else
end		

• async rst

always@(posedge clk or negedge rst)begin
	if(!rst)
	
	else
end

3 instantiated loop statement

genvar i;
generate
	for()begin:name
	instance
	end
endgenerate

4 function

1) does not contain any delay, timing or timing control logic
2) has at least one input variable
3) has only one return value, no output
4) does not contain non-blocking assignment statements
5) functions can call other functions, but cannot call tasks

	function [N-1,0] function_id(
		input	A,
		input	B
		);
		//outher_declaration
		//procedural statement
	endfunction 

- Examples of constant functions

parameter    MEM_DEPTH = 256 ;
reg  [log2(MEM_DEPTH)-1: 0] addr_width ; //可得addr的宽度为8bit
 
    function integer     log2;
    input integer     depth ;
        //256为9bit，我们最终数据应该是8，所以需depth=2时提前停止循环
    for(log2=0; depth>1; log2=log2+1) begin
        depth = depth >> 1 ;
    end
endfunction

- automatic function

Because when a general function is called, the local variables of the function will use the same storage space, so when two places are called at the same time, an uncertain value will be generated.

The automatic function can automatically allocate address space and can perform hierarchical access.

wire [16:0]          results3 = plusd(6);
function automatic   integer    plusd ;
    input integer    data_in ;
    begin
        plusd = (data_in>=2)? data_in * plusd(data_in-1) : 1 ;
    end
endfunction//阶乘运算

5 task

comparison point	function	Task
enter	The function has at least one input, and the port declaration cannot contain inout type	A task can have no or multiple inputs, and the port declaration can be of type inout
output	function has no output	Tasks can have no or multiple outputs
return value	A function has at least one return value	Task does not return a value
simulation moment	Functions always start executing at time zero	Tasks can be executed at non-zero time
sequential logic	Functions cannot contain any timing control logic	The always statement cannot appear in the task, but it can contain other timing controls, such as delay statements
transfer	Functions can only call functions, not tasks	Tasks can call functions and tasks
writing norms	A function cannot appear as a single statement, it can only be placed at the right end of the assignment language	A task can appear as a single statement in a statement block
simulation time unit	The function shares a time unit with the main module	Tasks can define their own simulation time units

https://www.runoob.com/w3cnote/verilog-task.html

task	task_name;
	//<端口名及数据类型说明>
	//procedural statement
endtask

call
task_name(port1,port2,...);

NOTES:

For tasks, the input defaults to wire, and the output defaults to reg. No need to explain again.

- for example

task and;
	input [N-1:0]	a;
	input [N-1:0] 	b;
	output [N-1:0]  c;
	#3 c = a & b;
endtask

- automatic task

task automatic test;

Two, testbench code

1 process

//1 port type
//2 initialization signal
//3 stimulate signal
//4 generate clock
//5 module instance
//6 stop

2 stop

    initial begin
        forever begin
            #100;
            if ($time >= 1000)  $finish ;
        end
    end

3 clock

Be sure to use 2.0, otherwise it will go wrong (accuracy problem)

always #(period/2.0) clk = ~clk;