ISCA'23 | June 17-21, the top conference in the field of architecture, with a new high admission rate! Scholars from Huazhong University of Science and Technology serve as Publicity Co-Chair!

ISCA, the full name of International Symposium on Computer Architecture, is the top conference in the field of architecture, jointly organized by ACM SIGARCH (Special Interest Group on Computer System Architecture) and IEEE TCCA (Technical Committee on Computer Architecture). Founded in 1973, ISCA is an old-fashioned architecture top meeting with a long history. Its scale has also expanded in the contemporary era when various applications and talents in the computer field are blooming everywhere, and big data and deep learning have triggered a new wave of development. ISCA is recommended by CCF as Class A conference, Core Conference Ranking recommends Class A* conference, H5 index is 56. ISCA is one of the top conferences in the field of computer system architecture. Many research results published by companies including Google, Intel, and NVIDIA on ISCA have been widely used in the semiconductor industry.

The number of ISCA submissions has fluctuated upwards, and has exceeded 400 in the past two years. However, the admitted articles have not changed much. The number of accepted articles in 2020 will rise to 77, the highest in history, and will drop to 67 in 2022. As far as the admission rate is concerned, ISCA has always been very low. Although there has been an upward trend in recent years, it has never exceeded the 20% mark. The difficulty can be imagined. But this year ISCA's acceptance rate soared to 21.24%, a record high.

Organizing committee information

The International Symposium on Computer Architecture (ISCA) is the leading forum for the discussion of new ideas and experimental results in computer architecture. The conference specifically seeks particularly forward-looking and novel proposals. In 2023, the 50th ISCA will be held at the Marriott World Center in Orlando, USA from June 17 to 21, 2023. ISCA 2023, an event of the FCRC, will be held from 17-23 June 2023 along with 13 other conferences. In addition, there are no domestic scholars in the Steering Committee and Program Committee of the ISCA Organizing Committee. Only in the Organizing Committee, Chencheng Ye from Huazhong University of Science and Technology serves as the Publicity Co-Chairs.

ISCA 2023 official website: https://iscaconf.org/isca2023/

Registration Fee Information

ISCA registration is divided into online and offline. The online registration fee is 100 dollars, and the offline registration starts at 430 dollars. The specific registration fee information is as follows:

For those who cannot attend ISCA in person, the registration fee is US $100.

Recruitment information

ISCA received a total of 372 submissions this year, and accepted 79, with an acceptance rate of 21.24%. The accepted papers are as follows

ML Systems

OliVe: Accelerating Large Language Models via Hardware-friendly Outlier-Victim Pair Quantization
FACT: FFN-Attention Co-optimized Transformer Architecture with Eager Correlation Prediction
Mystique: Enabling Accurate and Scalable Generation of Production AI Benchmarks
Accelerating Personalized Recommendation with Cross-level Near-Memory Processing
Understanding and Mitigating Hardware Failures in Deep Learning Training Systems
LAORAM: A Look Ahead ORAM Architecture for Training Large Embedding Tables
Optimizing CPU Performance for Recommendation Systems At-Scale

CPU Mircoarchitecture

Orinoco: Ordered Issue and Unordered Commit with Non-Collapsible Queues
SPADE: A Flexible and Scalable Accelerator for SpMM and SDDMM
DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations
μManycore: A Cloud-Native CPU for Tail at Scale
MESA: Microarchitecture Extensions for Spatial Architecture Generation
Imprecise Store Exceptions
Supply Chain Aware Computer Architecture

Security

ISA-Grid: Architecture of Fine-grained Privilege Control for Instructions and Registers
TEESec: Pre-Silicon Vulnerability Discovery for Trusted Execution Environments
Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense Schemes
Spy in the GPU-box: Covert and Side Channel Attacks on Multi-GPU Systems
Doppelganger Loads: A Safe, Complexity-Effective Optimization for Secure Speculation Schemes
Pensieve: Microarchitectural Modeling for Security Evaluation
All your PC are belong to us: Exploiting Non-control-transfer Instruction BTB Updates for Dynamic PC Extraction

Domain Specific Accelerators

HAAC: A Hardware-Software Co-Design to Accelerate Garbled Circuits
An Algorithm and Architecture Co-design for Accelerating Smart Contracts in Blockchain
FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations
MetaNMP: Leveraging Cartesian-Like Product to Accelerate HGNNs with Near-Memory Processing
RSQP: Problem-specific Architectural Customization for Accelerated Convex Quadratic Optimization
Flumen: Dynamic Processing in the Photonic Interconnect

Memory Systems

DRAM Translation Layer: Software-Transparent DRAM Power Savings for Disaggregated Memory
RowPress: Amplifying Read-Disturbance in Modern DRAM Chips
EMISSARY: Enhanced Miss Awareness Replacement Policy for L2 Instruction Caching
Write-Light Cache for Energy Harvesting Systems
Implicit Memory Tagging: No-Overhead Memory Safety Using Alias-Free Tagged ECC
On Endurance of Processing in (Nonvolatile) Memory

Emerging-Vision/Graphics/AR-VR

Instant-3D: Instant Neural Radiance Field Training Towards On-Device AR/VR 3D Reconstruction
K-D Bonsai: ISA-Extensions to Compress K-D Trees for Autonomous Driving Tasks
NeuRex: A Case for Neural Rendering Acceleration
Hardware Acceleration of Neural Graphics
Gen-NeRF: Efficient and Generalizable Neural Radiance Fields via Algorithm-Hardware Co-Design
EdgePC: Efficient Deep Learning Analytics for Point Clouds on Edge Devices

Emerging-Robotics

Energy-Efficient Realtime Motion Planning
RoSÉ: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation
RoboShape: Using Topology Patterns to Scalably and Flexibly Deploy Accelerators Across Robots

SSD

Venice: Improving Solid-State Drive Parallelism at Low Cost via Conflict-Free Accesses
ECSSD: Hardware/Data Layout Co-Designed In-Storage-Computing Architecture for Extreme Classification
Decoupled SSD: Rethinking SSD Architecture through Network-based Flash Controllers

GPU

R2D2: Removing ReDunDancy Utilizing Linearity of Address Generation in GPUs
SAC: Sharin g-Aware Caching in Multi-Chip GPUs