chance
The platform reminded me today that I have been creating for 3 years. If I don't remind myself, I don't feel anything. Three years is not long, and it is not short. As of today, I have published 213 articles and uploaded 117 resources on CSDN. The fields involved include: digital signal processing, FPGA design, IC design verification, radar signal processing algorithm simulation, etc.
In this summary ( 2022 is on the way~ ) I also mentioned the original intention of creation. Mainly I want to record my own learning process. There is a saying that is very good: a good memory is not as good as a bad pen. Today, with such advanced technology, I choose to continue my learning habits in the form of blogs. It is always good to record more. When recording and summarizing, it is also a good time to reflect on yourself and improve your technology. In addition, the blog content I recorded can also give some inspiration and help to students who are also in the early stages of learning. And technical exchanges can be realized through private messages or comments. It is unacceptable to me to work behind closed doors, so this method can really provide a good opportunity for learning and communication.
So, here I also want to say, all IC/IT technicians, those who have the habit of blogging and recording should continue to maintain it, because the records and accumulation of bit by bit technology will one day accumulate a lot and become a technical expert in a certain field /big cow. For those who haven’t blogged yet, let’s take the first step boldly. Don’t be afraid that the quality of the articles you post is not enough. What you need to know is that the first purpose of posting a blog is not for others to read, but to summarize the technology for yourself watch. After the washing of time, we can also slowly transform from a technical novice to a technical master. come on!
reward
Naturally, there are gains. The current number of fans counted by the platform is 8,379, the total number of visits exceeds 360,000, and the number of article collections reaches 3,285. This will also give me a lot of motivation, and motivate me to continue to make better blogs and share them with everyone.
In addition, I also received a lot of communication technology and comments that agree with me:
In addition to this, more colleagues joined the technical exchange group I created through the link at the end of the article:
daily
At this stage, I am still a graduate student (secondary research). In my spare time, I will still take the initiative to create some technical articles. Especially facing the problem of finding a job this year, I may share some experience in written test interviews as I progress in job hunting.
I believe that after graduation in the future, I will continue to create in my workplace.
Achievement
I am a person who often writes code. If I want to say what is the best code I have ever written, I may not be able to think of it for a while. But the code of the polling arbitrator written in Verilog recently impressed me. Here is the implemented code:
Original link, details: MediaTek 2024 IC design verification practice written test analysis
// ===================================================================================
// 功能：
// -1- Round Robin 仲裁器
// -2- 仲裁请求个数N可变
// -3- 加入lock机制（类似握手）
// -4- 复位时的最高优先级定为 0 ，次优先级：1 -> 2 …… -> N-2 -> N-1
// By：Xu Y. B.
// ===================================================================================
`timescale 1ns / 1ps
module Round_Robin_Arbiter #(
parameter N = 4 //仲裁请求个数
)(
input clock,
input reset_b,
input [N-1:0] request,
input [N-1:0] lock,
output reg [N-1:0] grant//one-hot
);
// 模块内部参数
localparam LP_ST_IDLE = 3'b001;// 复位进入空闲状态，接收并处理系统的初次仲裁请求
localparam LP_ST_WAIT_REQ_GRANT = 3'b010;// 等待后续仲裁请求到来,并进行仲裁
localparam LP_ST_WAIT_LOCK = 3'b100;// 等待LOCK拉低
// 模块内部信号
reg [2:0] R_STATUS;
reg [N-1:0] R_MASK;
wire [N-1:0] W_REQ_MASKED;
assign W_REQ_MASKED = request & R_MASK;
always @ (posedge clock)
begin
if(~reset_b)
begin
R_STATUS <= LP_ST_IDLE;
R_MASK <= 0;
grant <= 0;
end
else
begin
case(R_STATUS)
LP_ST_IDLE:
begin
if(|request) //首次仲裁请求
begin
R_STATUS <= LP_ST_WAIT_LOCK;
grant <= request & ((~request)+1);
R_MASK <= ~((request & ((~request)+1))-1 | (request & ((~request)+1)));
end
else
begin
R_STATUS <= LP_ST_IDLE;
end
end
LP_ST_WAIT_REQ_GRANT://处理后续的仲裁请求
begin
if(|request)
begin
R_STATUS <= LP_ST_WAIT_LOCK;
if(|(request & R_MASK))//不全为零
begin
grant <= W_REQ_MASKED & ((~W_REQ_MASKED)+1);
R_MASK <= ~((W_REQ_MASKED & ((~W_REQ_MASKED)+1))-1 | (W_REQ_MASKED & ((~W_REQ_MASKED)+1)));
end
else
begin
grant <= request & ((~request)+1);
R_MASK <= ~((request & ((~request)+1))-1 | (request & ((~request)+1)));
end
end
else
begin
R_STATUS <= LP_ST_WAIT_REQ_GRANT;
grant <= 0;
R_MASK <= 0;
end
end
LP_ST_WAIT_LOCK:
begin
if(|(lock & grant)) //未释放仲裁器
begin
R_STATUS <= LP_ST_WAIT_LOCK;
end
else if(|request) //释放的同时存在仲裁请求
begin
R_STATUS <= LP_ST_WAIT_LOCK;
if(|(request & R_MASK))//不全为零
begin
grant <= W_REQ_MASKED & ((~W_REQ_MASKED)+1);
R_MASK <= ~((W_REQ_MASKED & ((~W_REQ_MASKED)+1))-1 | (W_REQ_MASKED & ((~W_REQ_MASKED)+1)));
end
else
begin
grant <= request & ((~request)+1);
R_MASK <= ~((request & ((~request)+1))-1 | (request & ((~request)+1)));
end
end
else
begin
R_STATUS <= LP_ST_WAIT_REQ_GRANT;
grant <= 0;
R_MASK <= 0;
end
end
default:
begin
R_STATUS <= LP_ST_IDLE;
R_MASK <= 0;
grant <= 0;
end
endcase
end
end
endmodulelook forward to
This year is also the time to look for a job. In the future, I have two career plans:
1. Engage in a career in the direction of FPGA design verification
2. Engage in the occupation of ASIC chip design and verification
From the strength of possibility and willingness, I am more inclined to the second one: design and verify ASIC. Efforts to make a little contribution to the IC cause.
I also wish myself and my peers to find the job they want in this year's autumn recruitment. Come on, go, go, go!