Paper address: https://arxiv.org/pdf/2302.00386v1.pdf
github: https://github.com/meituan/YOLOv6/releases
I. References
Since the success of VGG in image classification tasks, convolutional neural network design has attracted extensive attention from academia and industry. At present, a large number of classic networks have been proposed, such as Inception and Resnet. These well-designed architectures lead to increasingly higher accuracy in image classification. In addition to manual design, recent neural network architecture search has also automatically designed several representative networks, such as Nasnet and AmoebaNet. While complex networks have brought success to vision tasks such as image classification, object detection, and segmentation, these networks may not achieve the appropriate accuracy-speed balance on deployment hardware.
Deep learning network design and deployment has 提高硬件效率been the focus of research. Traditional inference efficiency evaluation metrics are floating point operations (FLOPs) and number of parameters. However, these metrics cannot represent the relationship to hardware, eg 内存访问成本和I/O吞吐量. Figure 3 shows the relationship between computing power and memory resources. Therefore, this paper faces an important problem: how to design a友好于硬件的网络，以实现更好的准确性-速度平衡？