1. Custom FSM description
1. State description
State0: Sleep, get up and eat breakfast if the alarm clock rings, otherwise continue to sleep
State1: Eat breakfast, go to class after eating
State2: Go to class, if you want to have a meeting after class, go to the meeting, otherwise go to self-study
State3: self-study, lunch after the self-study meeting
State4: Have a meeting, have lunch after the meeting
State5: eat lunch, take a nap after lunch
State6: take a nap, if you want to exercise after taking a late nap, go to exercise, otherwise play games
State7: exercise, take a shower after exercise
State8: play games, take a shower after playing games
State9: Take a shower, eat dinner after the shower
State10: Eat dinner, and after dinner, if you want to go to self-study in the evening, go to self-study, otherwise watch a movie
State11: Evening self-study, go to bed after evening self-study
State12: Watch a movie, go to bed after watching the movie
2. Design code description
First define the module name, including input and output interfaces:
Then encode the defined 12 states:
Then there is the code for state transition directly according to the input control signal:
3. Simulation waveform description (screenshot + text annotation)
Test file code:
As shown in the figure, for the first day, there is a judgment statement that zot==4'b1011 will execute the following statement, that is, state11. At the beginning, all control signals are 0, and the state process of the first day will be state0 ->state1 ->state3 ->state5 ->state6 ->state8 ->state9 ->state10 ->state11 ->state0.
200ms after the state reaches state11, meet will be 1, and it will enter state4 at this time. When entering state6, the sport control signal is set to 1, so it will enter state7, and finally enter state12 and return to state0. So the second state process is state0 ->state1 ->state2 ->state4 ->state5 ->state6 ->state7 ->state9 ->state10 ->state12 ->state0.
See verification by simulation:
You can see that the red frame is the state transition of the first day, and the green frame is the state transition of the second day, which is consistent with the above analysis and correct.
2. EEPROM read and write code design and simulation
1. Code Description
1. Port
2. Status
Each state is represented by an 8-digit hexadecimal number. Compared with the data transmission on SDA in the above figure, each bit of data transmission has a corresponding state, and there are some waiting states.
3. SCL synchronization
The frequency of the clock is very high, reading and writing data cannot be carried out with the cycle of the clock, and the time required for the device to respond and read and write is much longer than the clock cycle, so the SCL synchronization method is used to synchronize the timing.
The SCL cycle is realized by clock cycle. One scl cycle is 30 clock cycles. Use div_cnt to record the number of clock cycles, 30 cycles
4. Status update
5. Judgment of read and write commands
The read and write commands are determined by inputting write_op and read_op through the port. These two signals are active at low level. The two registers wr_op and rd_op are used to reverse the input write_op and read_op, so that if there is a read or write command, wr_op or rd_op is 1, reset and end of operation (wr_opover) must be cleared, then use wr_op and rd_op to judge whether to read and write, here just replace the original low-level active signal with two high-level active signals .
6. Next state judgment
Byte Write : START + DEVICE +ACK + ADDR + ACK + DATA + ACK + STOP
Random Read : START + DEVICE + ACK +ADDR + ACK+START + DEVICE + DATA + NO ACK + STO
The next state update is at scl_tick (every 30 clk), the part underlined above is the same, regardless of reading and writing, the initial state update is to update the state in sequence according to the order of the underline above. At this time, the device address They are all 10100000 (write), when the ACK of ADDR is received, that is, W_AACK, it will decide what state to enter next according to wr_op and rd_op, wr_op will start to read data in state W_DATA; rd_op will go to WAIT_WTICK3, and then continue to START. After the operation, it needs to wait for a signal d5ms_over to return to idle, and the frequency of the control device should not be too high.
7. SCL synchronization implementation
In idle, waiting, operation end, start and other states, SCL is high level, so it is not necessary to clear SCL by clr_scl. In addition, clr_scl is only set to 1 at scl_ls (scl low level start), clear scl to 0, at scl_hs of 15 clk cycles, and then pull scl high to realize the SCL cycle
8. Implementation of SDA
The second half of the code is part of the implementation of SDA, because it is too long, so we analyze it piece by piece.
The following paragraph is the statement of control signals to realize SDA. These signals are set to 1 in the corresponding state and scl is in the center of the low level, telling SDA what to do. i2c_reg is used to temporarily store data on scl, and i2c_rlf is for reading and writing The data is used, the part used is in the next piece of code
The next step is to operate according to the control signal, put the corresponding operation data into i2c_reg, and prepare to transmit it to the SDA line. When i2c_rlf is 1, i2creg will be shifted to the left by one bit, because sda is unit wide, and the highest value of i2creg will be set every time. The bit is sent to sda, so the left shift is to send the data to sda one by one
Next is the control of sda output. sda enables the host to write data address, and the data is always 1. When the enable is 1, the device outputs the highest bit of i2creg by sda. Other response signals other than NOACK, as well as the read data, are sent from the slave to the sda line. At this time, the sda enable of the host is 0, and data cannot be sent
The following is the operation of reading data, using sda_wr control, reading data into read_data at the center of scl high level (when the data is stable), moving left to supplement sda, and updating read_data bit by bit with the data sent by sda, this When sda is the slave sending data
9. The operation is over, wait
The last is the waiting time after the operation is over. d5ms_cnt is used to record the clock cycle. When it is full, it will set d5ms_over to 1. In the part of the above state transition, it is this signal that finally enters the STOP state. After waiting for this signal, I2C will Back to idle.
Finally, there is no ACK processing part in this module. It just reads the signal from sda when the ACK should be received, and does not make a judgment. It may be handed over to the host.
2. TestBench code description
The main code of TestBench is as follows:
According to the above code, we can know that the read and write commands are determined by inputting write_op and read_op through the port. So the program writes first and then reads, and the waveform should be the same.
3. Simulation waveform description (screenshot + text annotation)
When SCL is high and SDA is a falling edge, the device starts to work. The device address is first written by the master, and then the data address is written. After each write, the slave will reply with an ACK signal to indicate receipt. The device address is the address of the slave EEPROM 1010000X, X is 0 means write, 1 means read, and when the device address is first written, X is all 0. To perform a write operation, the master only needs to send the data, and the slave sends an ACK response to reply that it has been received.
Perform a read operation and write the device address again, this time X is 1, indicating that the data will be read next, the slave will read the data, and the master will reply NOACK to the slave after receiving the data to indicate that it has received the data.
3. Experimental summary
Through this experiment, I learned a lot of knowledge, such as how to customize the state machine, the basic syntax of Verilog, how to write testbench test files, and how to use modelsim software for simulation testing. At the same time, I have a deeper understanding of the I2C protocol, and can elaborate on the meaning of the EEPROM code. This experiment has also greatly improved my coding ability, and I can also explain state transitions by analyzing state diagrams. At the same time, this experiment also encountered many difficulties, such as unfamiliarity with Verilog syntax, and doubts about the installation of modelsim software, etc., but they can be resolved by asking teachers and classmates for help