Talking about I2C knowledge

For embedded developers, I2C is something that is no longer familiar. In the field of electronic products, it is widely used.

Introduction

The I2C communication protocol (Inter-Integrated Circuit) was developed by Philps. Because it has few pins, simple hardware implementation, and strong scalability, it does not require external transceiver devices such as USART and CAN. It is now widely used in Communication between multiple integrated circuits (ICs) in a system.

I2C is mainly divided into SCL and SDA. SCL is the serial clock line, and SDA is the serial data line. Since it is used to transmit data, knowledge about its rate must be indispensable.

I2C speed

I2C rate is divided into three modes: standard, fast and high speed, and the three rates are as follows
Standard rate: 100Kbits/s
Fast rate: 400Kbits/s
Fast mode Enhanced: 1Mbit/s
High rate: 3.4Mbits/s

After talking about the speed, we will talk about I2C. The editor will introduce a group of I2C tested in the project.

I2C Timing

start and end

The I2c timing is divided into start and stop, all of which are controlled by the Master.
Start: SCL is high, SDA changes from 1 to 0.
Termination: SCL is high, SDA changes from 0 to 1.

Repeated Start Condition: Similar to the Start Condition, the Repeated Start Condition is sent before the Stop Condition. When the master wants to continue sending messages to the slave, a repeated start condition can be sent after a byte transmission is completed instead of a stop condition.

bit transfer of data

Each transmission of data is in units of bytes (8 bits), and the transmission of one byte requires 9 clock cycles.

The master device will transmit a data bit on the SDA line during each clock pulse generated on the SCL line, and the data bits will be transmitted in order from high bit to low bit. The data on SDA must be stable when SCL is high level, and the high and low level inversion of data occurs when SCL is low level.

It can be seen from the figure below that
the level conversion of SDA always occurs when SCL is low.
When SCL is high, the SDA level does not change.

In I2C, the first eight bits are often sent by the Master. Among them, the first seven bits are address bits. The eighth bit is the read and write bit.

There are two types of I2C address bits, 7bit and 10bit. For 7bit addresses, it supports addressing up to 127 devices (the actual situation should consider the load capacity, and the total capacity is not allowed to exceed 400PF). For 10bit addresses, up to 1023 devices are supported.

The 10bit address protocol is compatible with the 7bit address protocol. Most of the currently used addresses are 7 bits, and the eighth bit is the read and write bit. When the eighth bit is 0, it means write. When it is 1, it means read.

In the data sheets of some chips, we often see descriptions like the following
I2C slave address: (W)OX58H, ®OX59H
W stands for writing, R stands for reading.
The picture above represents 0X58. Convert from hexadecimal to binary.
0X58=0101 1000

Observe that the first eight digits are completely consistent.

ACK and NACK

The biggest feature of I2C is the existence of a complete response mechanism. When the slave receives the data from the master, it will reply with a response signal to notify the master that "I have received it".

The first eight address + read/write are sent by Master. In the ninth clock cycle, the Master releases the bus and hands over the control of the bus to the slave. However, under the action of the pull-up source, the bus is at a high level at this time. If the slave receives the data sent by the master as 0 , pull SDA low to indicate a response.

A brief description is:
Slave works, it is ACK. The ninth bit level is low level.
Slave does not work, it is NACK. The ninth bit level is high level.

When the Master confirms that the Slave is the Slave it wants, it starts to transmit 8-bit data bytes. Wherein, each transmission of 8-bit data will be followed by a response signal generated by the host. Until the transmission finally enters the termination condition, I2C stops the data transmission and enters the idle state.

According to reading and writing, we can roughly divide the transmission of I2C into the following two states:

I2C write process

1. Master sends I2C 7-bit address and write operation bit, waiting for ACK.
2. Slave sends ACK.
3. Master sends register address bit, waiting for ACK
4. Slave sends ACK
5. Master sends data. i.e. write register data
6. Slave sends ACK
7. Repeat steps 5 and 6 to write multiple register data
8. Master initiates STOP
   

I2C read process

1. Master sends I2C 7-bit address and write operation bit, waiting for ACK.
2. Slave sends ACK.
3. Master sends register address bit, waiting for ACK
4. Slave sends ACK
5. Master re-executes the start condition
6. Master sends I2C 7-bit address and read operation bit, waiting for ACK.
7. Slave sends ACK
8. Slave sends 8-bit data, which is the value in the register
9. Master sends ACK
   and repeats steps 8 and 9, multiple registers can be read
   until Master finally sends NACK and enters termination.
   
   
   The waveform captured in the project is attached as follows
   

hardware circuit design

The hardware circuit design of I2C is not complicated.

The IO port of I2C, because it is an open drain, does not support high-level output. To have a high level, an external pull-up source must be provided.

The selection of pull-up resistors is often 1K-10K. The selection of the resistor often has a certain influence on the rising edge of the signal.

Generally, the driving current of the IO port is 2-4 mA. The pull-up source is Vdd. At the same time, the turn-on voltage of OC and OD is often around 0.4V.

Therefore, it can be known by calculation
that Rmin=(Vdd-0.4)/0.003A
Rmax=(T/0.874)*C
where, when the I2C rate is 100Kbits/s, T=1us. When the rate is 400Kbits/s, T=0.3us. When the rate is 1Mbits/s, T=0.12us.
(Note: In some circuits, the MCU will integrate the pull-up, and what we finally see is that the peripheral circuit does not need a pull-up source)

Frequently asked questions about waveforms

About several types of common problems of I2C in Xiaobian's previous projects

1. The SCL rise time tr is
   greater than the datesheet standard. If the rise time is large, it means that compared with the standard, the rise is relatively gentle and the driving ability is weak. This kind of problem is often caused by the unreasonable selection of the resistance value of the pull-up resistor. The load itself contains capacitance. If the pull-up resistor is too large, the RC delay circuit will cause the rise to become gentle.
   Solution: reduce the pull-up resistor; adjust the drive capability by software.

2. The SDA SCL waveform is slightly raised as a whole, and the low level is difficult to approach 0V, or even exceed 0.4V
   . There are two possibilities.
   A: During the test, the oscilloscope probe was not calibrated, which caused such problems during the test.
   B: The pull-up resistor is selected too small and the drive current is too large.
   Solution: Calibrate the oscilloscope; appropriately reduce the resistance of the pull-up resistor.

3. Glitch on SDA signal.
   The editor has encountered it in previous projects. This kind of problem must be paid attention to. Each high level and low level of I2C has a special meaning. If the low level of the address bit, write or response bit is mistakenly recognized as a high level due to glitches, it will affect the normal operation of the slave. work.

Solution: PCB traces cover the ground; SDA signal series small resistors.

4. I2C address conflict
   In hardware design, we often hang multiple groups of devices on a group of I2C. Sometimes, if you don't pay attention, you will hang two devices with the same address on the same group of I2C.

Solution: Some chips have AD pins, such as smart pa chips, which can change the address according to AD grounding or power supply. Or after returning to the board, manually rework.