Learning about the bus (1): Getting Started

1-AMBA overview

AMBA (Advanced Microcontroller Bus Architecture) Advanced Microprocessor Bus Architecture

Defines the communication standard for high-performance embedded microcontrollers, can integrate RISC processors (reduced instruction set processors) in other IP cores and peripherals, it is the "digital glue" that effectively connects IP cores, and is ARM important components of a reuse strategy;

It is not an interface between the chip and the peripherals, but an interface between the ARM core and other components on the chip . For example, Xilinx's Zynq chip is the connection path between ARM and FPGA. It mainly includes:

• AHB (Advanced High-performance Bus) Advanced High-performance Bus

• ASB (Advanced System Bus) Advanced System Bus - rarely used

• APB (Advanced Peripheral Bus) Advanced Peripheral Bus

• AXI (Advanced eXtensible Interface) advanced extensible interface

These contents together define a set of standards for on-chip communication designed for high-performance SoC;

AHB is mainly a bus designed for high-efficiency, high-bandwidth and fast system modules , which can connect high-efficiency modules such as microprocessors, on-chip or off-chip memory modules, and DMA;

APB is mainly used in low-speed and low-power peripherals, which can optimize power consumption and complex interfaces for peripheral devices; APB provides a communication bridge between AHB and low-bandwidth peripheral devices, so APB is AHB or ASB Secondary expansion bus;

AXI: High speed, high bandwidth, pipelined interconnection, one-way channel, only the first address is required, read and write in parallel, support out-of-order, support non-aligned operations, effectively support peripherals with high initial delay, and have a lot of connections ;

Performance comparative analysis of several AMBA buses:

2- The difference and connection between AHB, AXI and APB

AHB is an advanced high-performance bus , AXI is an advanced scalable interface , and APB is an advanced peripheral bus;

Both AHB and APB are single-channel buses, which do not support parallel reading and writing ; while AXI is a multi-channel bus, which is divided into five channels in total, which can realize parallel reading and writing ;

Both AHB and AXI are multi-master/slave devices, and the allocation of bus control rights is realized through an arbitration mechanism ;

The APB is a single-master device with multiple slave devices , and its master device is the APB bridge , which does not have an arbitration mechanism ;

In terms of data operations, AHB and AXI support burst transmission , but APB does not; in addition, AXI supports data unaligned operations , but AHB does not;

3-AHB bus (multi-master/slave-arbitration mechanism)

The power of the AHB bus is that it can connect the microcontroller (CPU) , high-bandwidth on-chip RAM , high-bandwidth external memory interface , DMA bus controller , and various AHB interface controllers to form an independent complete The SOC system can also connect to the APB bus system through the AHB-APB bridge. It mainly includes the following four parts:

Master AHB main controller : The main controller can initialize, read and write through the address and control information, and only one Master will be activated at the same time;

Slave AHB slave device : A slave device usually refers to a passive device that responds to the read and write control operations issued by the master controller in its address space, and returns success, failure or waiting status to the Master to complete the data transmission control;

Arbiter AHB arbiter : The arbiter ensures that only one master controller has the bus control authority on the bus at the same time according to the user's configuration, so as to ensure that only one Master is working on the bus at a time; there can only be one arbiter on the AHB bus;

Decoder AHB decoder : responsible for decoding the address and providing a chip select signal to each Slave; the AHB bus can only have one decoder;

Each AHB needs 1 arbiter and 1 central decoder, and there is only one!

1-AHB basic signal

HADDR: 32-bit system address bus;

HTRANS: M indicates the transmission status, NONSEQ, SEQ, IDLE, BUSY;

HWRITE: transmission direction 1-write, 0-read;

HSIZE: transmission unit;

HBURST: the burst type of transmission;

HWDATA: write data bus, write from M to S;

HREADY: S responds to M whether the read and write operation transmission is completed, 1-transmission is completed, 0-need to extend the transmission cycle. It should be noted that HREADY is a signal on the bus, which is the input of M and S; at the same time, each S needs to be output from HREADY. So there will be two HREADY signals for S, one input from the bus, and one output to the multiplexer by itself;

HRESP: S responds to the current transmission status, OKAY, ERROR, RETRY, SPLIT;

HRDATA: read data bus, read from S to M;

2-AHB Basic Transport

1 - two stages

Address cycle (AP), only one cycle

Data cycle (DP), how many cycles are required depending on the HREADY signal

2- Pipeline transmission

An address cycle followed by a data cycle

The characteristics of AHB burst transmission and AXI burst transmission

The AHB protocol requires all addresses for a burst transfer , and the corresponding relationship between addresses and data locks. The next burst transfer must be completed before the previous transfer;

AXI only needs the first address of a burst , and can send multiple burst transmission first addresses continuously without waiting for the completion of the previous burst transmission, and multiple data can be interleaved, which greatly improves the utilization of the bus;

Both the AHB bus and the AXI bus are suitable for high-performance, high-bandwidth SoC systems , but AXI has better flexibility, and can read and write channels in parallel without affecting each other ;

More importantly, the AXI bus supports out-of-order transmission, which can effectively use the bandwidth of the bus and balance the internal system. Therefore, in the SoC system, the AXI bus is used as the main bus, and the AHB bus and the APB bus are connected through a bridge , which can increase the flexibility of the SoC system and more reasonably allocate different feature IPs to the bus;

4-APB bus (single master and multiple slaves)

APB is an optimized, low-power, streamlined interface bus that can support a variety of slow peripherals ;

It is mainly used in low-bandwidth peripherals, such as UART and I2C . Its architecture is not like the AHB bus, which is a multi-master architecture. The only master of the APB bus is the APB bridge (connected to AXI or APB ), so no arbitration is required. Some Request/grant signals.

**The APB bus protocol includes an APB bridge,** which is used to convert the control signals on the AHB and ASB buses into signals available on the APB slave device controller. All peripherals on the APB bus are slave devices, and these slave devices have the following characteristics:

• a Receive a valid address and control access
• b When peripherals on the APB are inactive, these peripherals can be placed in a 0-power state
• The c decoder can provide output timing through the strobe signal (non-locking interface)
• d Executable data write when accessing

The protocol of APB is also very simple, it is not even a pipeline operation , and a read or write operation is completed at a fixed two clock cycles .

Its characteristics include: two clock cycle transmission, no need for waiting period and response signal, simple control logic, only four control signals.

The transmission on the APB can be illustrated by the state diagram shown in the figure:

• 1. The system is initialized to the IDLE state. At this time, there is no transmission operation, and no slave module is selected;

• 2. When there is transmission to be carried out, PSELx=1, PENABLE=0, the system enters the SETUP state, and will only stay in the SETUP state for one cycle. When the next rising edge of PCLK arrives, the system enters the ENABLE state;

• 3. When the system enters the ENABLE state, keep the PADDR, PSEL, and PWRITE in the SETUP state unchanged, and set PENABLE to 1. The transmission will only be maintained for one cycle in the ENABLE state, and it will be completed after passing through the SETUP and ENABLE states. After that, if there is no transmission to be performed, it will enter the IDLE state and wait; if there is continuous transmission, it will enter the SETUP state;
  

• write transfer

• read transfer

5-ASB bus

The ASB bus is mainly used for high-performance system modules.

ASB is an optional system bus on chip designs that can be used for high-performance features not required by AHB .

ASB also supports high-performance processors, on-chip memory, and off-chip memory to provide interfaces and slow peripherals. High performance, data transmission, multi-bus master controller, burst and continuous transmission. The ASB bus is a high-performance bus protocol located on the APB bus architecture . It has the following characteristics:

• a Burst continuous transmission
• b single-pipeline data transfer
• c Multi-bus master controller

6-AXI Protocol Introduction

As an ARM standard interface protocol, AXI is mainly used in on-chip system interconnection design. Interaction between different IPs can be realized through a standard interconnection bus. Convenient protocol conversion can be realized between each protocol in the chip, and all IP communications within the system can be completed.

• AXI is divided into 5 independent transmission channels, namely AR, R, AW, W, and B channels.
• AR is the read address channel, which transmits the address of the read operation and the corresponding control information;
• R is the read data channel, which transmits the readback data corresponding to the AR channel and also transmits the response information of the slave;
• AW is the write address channel, which transmits the address of the write operation and the corresponding control information;
• W is the write address channel, which transmits information related to write data;
• B is the write response channel, which transmits the write response information returned by the slave;

Five channels are independent channels, which can greatly improve system transmission performance. It should be noted that there are 2 channels for read operations and 3 channels for write operations. There is no separate response channel in the read channel. The read response and read data share a channel for transmission. Both are returned by the slave and there is no need to separate them.

7- AMBA-based System-on-Chip

Most of the modules (including processors) hanging on the bus are only functional modules with a single attribute: master module or slave module . The main module is a module that sends read and write operations to the slave module, such as CPU, DSP, etc.; the slave module is a module that accepts commands and responds, such as on-chip RAM, AHB/APB bridge, etc. In addition, there are some modules that have two attributes at the same time. For example, direct memory access (DMA) is a slave module when it is programmed, but it must be a master module when the system reads and transfers data .

If there are multiple master modules on the bus, an arbiter is needed to decide how to control the access of various master modules to the bus . Although the arbitration specification is part of the AMBA bus specification, the specific algorithm used is determined by the RTL design engineer, and the two most commonly used algorithms are the fixed priority algorithm and the round robin algorithm . There can be up to 16 master modules and any number of slave modules on the AHB bus. If the number of master modules is greater than 16, an additional layer of structure is required (for details, refer to the Multi-layer AHB specification introduced by ARM).

The APB bridge is not only the only master module on the APB bus , but also the slave module on the AHB system bus . Its main function is to latch the address, data and control signals from the AHB system bus, and provide two-level decoding to generate the selection signal of the APB peripheral equipment, so as to realize the conversion from the AHB protocol to the APB protocol.

Introduction and comparison of AMBA, AHB, APB, and AXI buses

Next, let's take a look at each bus type, the whole bus series! ! !

8-What is the difference between the AMBA AHB protocol and the AXI protocol

• AHB : Advanced High-performance Bus

• AXI : Advanced Xtensible Interface

AHB is one of the protocols of AMBA. If we look at the evolution history of the AMBA protocol, we will be amazed that such an original thing is still popular now.

What is the difference between the AMBA AHB protocol and the AXI protocol?

But obviously, if you want to engage in processor or SoC research and development, it is not enough to just understand AHB. With the increasing demand for chip computing capabilities in the information society, the AHB protocol has been unable to meet the bandwidth requirements of these actual services.

At this time, the AXI protocol came into being, and its main feature is to support 'outstanding' transactions, that is, the ability to initiate another transaction when one transaction has not been completed . Although the AHB protocol supports "'split'" transmission, the effect is not as good as the 'outstanding' ability of AXI.

Here are some differences between the AMBA AHB and AXI protocols for comparison:

• 1、

  • AHB has 1 address channel, 1 read data channel, and 1 write data channel;
  • AXI has 1 read address channel, 1 write address channel, 1 read data channel, and 1 write data channel. 1 write response channel, which has a total of 5 parallel channels.

• 2、

  • AHB does not support "outstanding";
  • AXI support "outstanding"

• 3、

  • If the timing cannot be met in AHB, it cannot be beat in the agreement;
  • In AXI it is possible to tap in the path of any of these 5 lanes, which facilitates higher clock frequencies.

• 4、

  • There are fewer connections between AHB master and slave;
  • Since AXI has 5 parallel lanes, it has more wires, which can cause backend routing congestion.

• 5、

  • AHB does not support side-band;
  • AXI supports side-band (using the AxUSER field in AXI)

• 6、

  • AHB does not support QoS;
  • AXI supports QoS

• 7、

  • AHB burst length is fixed (1/2/4/8, except INCR type), as long as it does not cross the 4K boundary;
  • The burst length in AXI can be _{any value in 1 16 (the incr type in AXI4 can support 1} 256)

• 8、

  • The AHB "INCR" type can have any length and does not need to be specified at the beginning of the burst transmission;
  • AXI INCR type transmission needs to specify AxLEN at the beginning of burst transmission

• 9、

  • AHB is order-preserving (the order of receiving the response and initiating read and write is the same), because only one read-write transaction request is executed at a time in the AHB protocol;
  • AXI supports multiple "outstanding", different AxID requests may be out of order, but the same AxID requests are still in order

• 10. AHB has lower power consumption than AXI

• 11、

  • AHB does not support Write Strobe;
  • AXI supports Write Strobe

• 12、

  • AHB supports Lock transmission;
  • AXI3 supports Lock transmission, AXI4 does not support Lock transmission

• 13、

  • AHB does not support Exclusive transmission;
  • AXI supports Exclusive transmission

Reference content:
AMBA, AHB, APB, AXI bus introduction and comparison

What is the difference between the AMBA AHB protocol and the AXI protocol?