Chapter 7 Improvement of actual combat projects and improvement of resume
18. SD card storage audio WAV playback (below)
Further, we analyze the timing logic design of the wav_play module in combination with the schematic diagram in Figure 1. You can clearly see that in the Right justified and master-slave clock modes, WM8731 sends the left channel first and then the right channel data. Here It needs to be emphasized that 4 points are also problems that have troubled the author for a long time:
1. The audio data in WAV format adopts 16Bit two-channel encoding format, which is equivalent to a basic audio data unit of 32Bit, which is why the 4-byte data read in the SD card sector is spliced together and then stored. into the FIFO, mainly for the convenience of data splitting of the wav_play module;
2. In this routine, we choose Right justified, main clock, and default 32bit mode. Notice that it is clearly stated in the manual that in main clock mode, DACLRC/ADCLRC outputs 64 BCLK clock cycles, that is, 32 BCLK high power Flat, 32 BCLK low levels;
3. In the Right justified and default 32bit mode, the first 32 BCLKs correspond to the high level of DACLRC/ADCLRC. At this time, the 16-bit data of the left channel should be input in the last 16 BCLKs, and the last 32 BCLKs correspond to the DACLRC/ADCLRC The low level of ADCLRC, at this time, the 16-bit data of the right channel should be input in the last 16 BCLKs, and the first 16 BCLKs of the corresponding left and right channels can be filled with zeros, and the data of DACDAT/ADCDAT should be in BCLK Clock falling edge update;
4. Note that the 16-bit dual-channel encoding format under WAV is: low byte of left channel data, high byte of left channel data,
Right channel data low byte, right channel data high byte, and the encoding format of WM8731 in Right justified, default 32bit mode is: left channel data high byte, left channel data low byte, right channel The high byte of data and the low byte of right channel data, so the 32-bit data read from the FIFO by the upstream wav_query module needs to be spliced in the program to reconstruct the data of the left and right channels.
Figure 1 Description of WM8731 in Right justified and master-slave clock modes
Table 1 shows the signal list of the wav_play module. In this module, we first split the 32-bit data read from the FIFO by the upstream wav_query module into 32-bit left channel data and 32-bit The right channel data is finally sent to DACDAT bit by bit under the action of BCLK and ADCLRC according to Right justified, main clock, and default 32bit mode.
Obviously, the CLK of this module corresponds to a 50Mhz clock much faster than BCLK, and can capture the falling clock edge of BCLK and the rising clock edge of ADCLRC, where wav_data and wav_data_vld correspond to the data signal and data indication signal of the upstream module respectively, and wav_playrdy is used as a read preparation The signal is instantiated to the upstream wav_query module to stimulate the read enable signal of the FIFO, as shown in Figure 2 is the code design of the WAV audio playback module.
| Signal list |
||
| Signal name |
I/O |
bit width |
| clk |
I |
1 |
| rst_n |
I |
1 |
| wav_bclk |
I |
1 |
| wav_adclrc |
I |
1 |
| wav_data |
I |
32 |
| wav_data_vld |
I |
1 |
| wav_playrdy |
O |
1 |
| wav_dacdata |
O |
1 |
Table 1 wav_play module signal list
Figure 2 Code design of WAV audio playback module
As shown in Table 2 and Table 3, they are the signal lists of config_wm8731 and i2c_wm8731 modules. Obviously, we need to initialize WM8731 before the chip can work according to our ideas. The config_wm8731 module stores 10 register addresses and parameter values, and the i2c_wm8731 module stores The timing logic of the entire IIC configuration is realized, and 10 registers are configured in sequence. After the IIC initialization is completed, the initial completion is indicated by the i2c_config_done signal, as shown in Figures 3 and 4, which are the code designs of the two modules.
| Signal list |
||
| Signal name |
I/O |
bit width |
| lut_index |
I |
4 |
| lut_data |
O |
24 |
| lut_size |
O |
4 |
Table 2 config_wm8731 module signal list
| Signal list |
||
| Signal name |
I/O |
bit width |
| clk |
I |
1 |
| rst_n |
I |
1 |
| i2c_config_size |
I |
4 |
| i2c_config_data |
I |
24 |
| i2c_sda |
I/O |
1 |
| i2c_scl |
O |
1 |
| i2c_config_index |
O |
4 |
| i2c_config_done |
O |
1 |
Table 3 i2c_wm8731 module signal list
Figure 3 Code design of WM8731 initialization register value module
Figure 4 Code design of WM8731 initialization register setting module
As shown in Figure 5, the code design of the top-level module for storing audio WAV playback in the SD card, you need to instantiate the relevant signals of each module together, in this routine, first of all, we have stored many first WAV formats in the SD card Then press the button KEY1, the FPGA will traverse each sector in turn according to the sector of the SD card until it finds the song in the WAV file header format, and the audio data in the WAV format will be configured according to the Right justified, main clock, and default 32bit mode of WM8731 Play the song, and then press the key KEY1 after playing a song, and the FPGA will search for the next song in the WAV file header format in the sector of the SD card, and continue to play the next song after finding it.
In order to facilitate debugging and observation, here the author also adds the key signals of each module to the ILA IP core. At the same time, LED0 is lit to indicate that the SD card and WM8731 are initialized, and LED1 is blinking to indicate that the audio data in the SD card is currently being played. After inserting the SD card, you can observe that the onboard LED0 lights up. Press the button KEY1 and soon the onboard LED1 will flash continuously. Beautiful battle song Counting Stars.
Figure 5 SD card storage audio WAV playback top-level module code design
SD card music WM8731 play