Analysis of segment page storage mechanism of memory addressing

Published on 2017-05-05 | 0 | Views: 486

background

When learning the operating system course, I have been exposed to the segmented page management mechanism of the operating system more than once, but I have only tasted it, and I don’t know why the operating system has this mechanism. Now that time has passed for a long time, the principle and implementation mechanism behind this mechanism have been forgotten for a long time. . Recently, I am looking at the knowledge of the operating system, so as to record my own understanding.

To understand the development of the segment page management mechanism, we have to start with the addressing mode of the early processors.

The development history of memory addressing mode

First, briefly introduce the concept of memory addressing. Modern computers are based on von Neumann's architecture. This architecture is centered on storage. That is to say, the premise of all operations is to first obtain data from memory. , so memory addressing technology represents computer technology to some extent.

direct addressing

In the early stage of processor development, Intel Corporation launched the first 8-bit processor - 8080. Its memory addressing method is simple and rude, and the program is absolutely positioned to the memory address in the form of hard coding. Programs in this case have obvious disadvantages: weak controllability, difficult to relocate, difficult to maintain, etc.

section

Soon, in another processor 8086 introduced by Intel, its addressable space reached 1M, that is, the address line was extended to 20 bits. Since it was difficult to manufacture 20-bit registers at that time, in order to be able to use 16-bit registers on the basis of Addressing the 20-bit address space introduces an important concept - 段the address of the segment is stored in the register, in other words, the 1M space is divided into several 64K (16-bit register addressable) segments for management. So the memory addressing of the segmentation mechanism in the 8086 is:

1	Segment base address shifted left by 4 bits + offset = physical address

In order to support the segmentation mechanism well, the 8086 processor provides special 16-bit registers for the code segment, data segment, and stack segment used by the program to store the segment base addresses of these segments. After the segmentation mechanism is introduced, the address of the program no longer needs to be hard-coded, and debugging errors are easier to locate. At the same time, more importantly, it supports a larger memory address space.

Paging and virtual memory

The paging mechanism first appeared in the 80386 processor, which was a major breakthrough in the memory addressing method and had a great impact on later computer systems. 虚拟内存The addressing space of the 80386 processor reaches 32 bits, and the paging mechanism is introduced in order to cooperate with the technology. Next, we will briefly talk about the virtual memory technology.

In simple terms, 虚拟内存technology allows programs to use more memory than the computer's actual memory . To give a simple example, when running a large game, it needs 5G memory, but a 32-bit notebook supports a maximum of 4G memory, and the von Neumann system tells us that when the program is running, the program needs to be loaded into the memory It can only run in the middle of the game, so can't this game be played? No, this program can be run with the help of virtual memory technology, but it may get stuck.

Virtual memory technology is essentially a technology that maps part of the hard disk space into memory, so that the memory space that programs can use becomes larger. The simple way is that if the address accessed by the program is not in the memory (placed in the external disk space), the program content of the disk space corresponding to the access address needs to be loaded into the memory, and the old program content may be faced during the loading process. replacement. How to conveniently manage these 置换or 加载other content? The concept introduced by the operating system 页, a page is a storage unit, generally 4K in size.

Having said that, can you 段机制manage these replaced and loaded content? Because the size of the segment is variable, it is inconvenient to transfer the virtual space of the entire segment size between the memory and the disk. A smaller and more flexible storage unit-page is needed, and the mechanism for managing swapping in and out is called 页机制.

After the paging mechanism is introduced, the address converted through the segment mechanism is only an intermediate address—a linear address, and the linear address needs to be converted into an actual physical address through the page mechanism. Summarize the memory addressing process, the conversion process from the logical address used in the program to the final physical address:

1	Logical address --> (segmentation mechanism) linear address --> (paging mechanism) physical address

Analysis of memory addressing process

Briefly introduce the development process of operating system memory addressing, and then analyze the process of segmentation and paging mechanism memory addressing in detail. First, let’s briefly talk about the concepts of logical address, linear address, and physical address:

Logical address: the address of an operand or an instruction in the program code
Linear address: virtual address can map 4G memory space (product of paging mechanism, logically continuous)
Physical address: Corresponds to the electrical signal sent by the processor's pin to the memory bus

Detailed segmentation mechanism

The logical address used in the code consists of two parts:

段选择符: 16-bit long field
段内偏移地址: 32-bit long field (maximum segment size is 4GB)

In order to quickly find 段选择符the location of the specified segment, the processor provides segment registers ( cs, ss, ds, es, fs, gs). Compared with the 8086, the 80386 adds new fsand gs additional segment registers, mainly to reduce es the burden on this register. .

It is worth noting that cs the register contains a 2-bit field to specify the privilege level DPL of the current CPU, 3 is the user mode, and 0 is the kernel mode.

segment descriptor

As mentioned earlier 段选择符, it is a 16-bit field with the following format:

15 ~ 3 digits: Index index number
2 bits: TI flag, indicating that the segment descriptor is in GDT (TI=0) or LDT (TI=1)
1 ~ 0 bit: RPL flag, the privilege level of the requester

段选择符The information of the segment can be indexed by the index number in it 段描述符represented by 8 bytes and 段描述符stored in 全局描述符表(GDT) and 局部描述符表(LDT). Similarly, the addresses of GDT and LDT are also stored in registers. Usually, when the system is initialized, the gdtr control register is initialized and the address of the GDT table is written. If each process needs its own additional segment besides storing GDT, it can be created. One LDT, write LDT the address of the table into ldtr the register.

Quick Access Segment Descriptor

Because only the address is stored in the segment register ,段选择符 the actual index needs to look up the GDT or LDT table. In order to speed up the conversion process from logical address to linear address, 80x86 provides an additional non-programming register, that is, whenever a register is loaded, the corresponding memory is loaded into this non-programming register.段选择符段描述符段选择符段描述符

In this way, when converting the linear address for the logical address of that segment, it is not necessary to access the GDT or LDT table, but directly refer to the 段描述符non-programming register storing this.

The process of address translation under the segmentation mechanism

A logical address consists of 段选择符and 段内偏移组成, when converted to a linear address, the segmentation unit performs the following operations:

First check 选择符the TI field of the segment to determine whether the segment 段描述符is stored in GDT or LDT
段选择符Then indexed by the Index in the actual段描述符
Index to the actual 段描述符address ✖️8, plus gdtr or ldtr the value in the register. This process completes 段the calculation of the starting position
Finally, add the calculated result to the logical address 段内偏移to get the linear address

Segmentation in Linux

Linux uses segmentation in a very limited way, preferring to use paging to manage memory because:

Memory management is simplified when all processes use the same segment registers, i.e. they can share the same set of linear addresses
Linux is designed to be portable to most platforms, however RISC has limited support for segmentation

The segmentation mechanism is used on Linux running on the 80x86 platform, and the corresponding segment selector is defined by defining four macros

__USER_CS : user mode code segment selector
__USER_DS : user mode data segment selector
__KERNEL_CS : Kernel mode code segment selector
__KERNEL_DS : Kernel mode data segment selector

That is to say, when addressing the kernel code segment, you only need to load the value of __KERNEL_CS into cs the segment register. cs The RPL value specified by the segment selector in the segment register indicates whether the current process belongs to the user mode or the kernel mode. .

For the GDT table, each CPU corresponds to a GDT table in Linux, all GDTs are stored in it cpu_gdt_table , and the addresses and sizes of GDTs are stored in cpu_gdt_descr an array, which will be initialized before the system starts.

Detailed paging mechanism

The paging mechanism mentioned above is introduced to cooperate with the virtual memory management in the operating system. The purpose of the paging mechanism is to convert linear addresses into physical addresses.

basic concept

Briefly talk about the concept of 页, 页框,页表

Page: Corresponding to the linear address, the linear address is divided into groups of fixed size, called pages, and the page size is generally 4K
Page frame: Corresponding to the physical address, the physical address is RAM, which is divided into fixed-size page frames, and each page frame corresponds to an actual page
Page table: A data structure used to map pages to specific page frames

regular pagination

Because the size of each page is 4KB, in order to map 4GB of physical space, there will be 1MB (2^20) mapping entries in the page table, and it is unacceptable to save such a large page table entry for each program , so the concept of multi-level page table is introduced, also known as 页目录.

That is to say, the conversion process of the linear address needs two steps. First, it searches to 页目录find the specific page table, and then searches the page table to find the specific page. If this page does not exist in RAM, that is, a page is missing, it will also trigger a page fault interrupt and apply for paging; if there is RAM, the conversion from linear address to specific physical address can be completed.

In the paging mechanism, each active process must have a page directory. It is not necessary to allocate RAM for all the page tables of the process. It is only allocated when it is actually used. This will be more efficient. The address being used by the process is stored in the 页目录register cr3 .

Linear Address Field Analysis

The linear address is divided into 3 parts, as follows:

Directory: Determine the directory entry in the page directory, 10 bits in size
Table: Determine the entry in the page table, 10 bits in size
Offset: the relative position of the page frame

Because the Directory and Table fields are both 10 bits in size, there are as many as 1024 entries in both the page directory and the page table. The data structure of the page directory and page table is similar, and both contain the following fields:

Present flag: 1 (page in main memory) 0 (not in main memory, causing page fault interrupt)
Accessed flag: This flag is set whenever the paging unit addresses the corresponding page frame
Dirty flag: Applies only to page table entries, this is set whenever a page frame is written
Read/Write flag: access permission with page or page table
User/Supervisor flag: Contains the privileged level of the access page or page table
PCD and PWT flags: control how hardware caches handle pages and page tables
Page Size flag: only used for page directory entries, if set to 1, then the size of the page frame is 2MB or 4MB
Global flag: only used for page table entries, preventing commonly used pages from being flushed out of the TLB cache

Translation Lookaside Buffer TLB

In addition to the internal hardware cache, it also includes a translation lookaside buffer (TLB) cache to speed up translation of linear addresses. When a linear address is used for the first time, the corresponding physical address is calculated by slowly accessing the page table in RAM, and the physical address is stored in the TLB entry so that the next reference to the same physical address can be quickly of get converted.

In a multiprocessor, each CPU has its own TLB. When the CPU's cr3 registers are modified, then all entries in the TLB become invalid because the current ones are new ones 页目录.

Paging in Linux

Two-level page tables are sufficient for 32-bit systems, but in order to support 64-bit systems, multi-level page tables need to be introduced. Linux has introduced four-level page tables since version 2.6.11:

page global directory
page parent directory
page middle directory
page table

For 32-bit systems that do not enable physical address extension, two-level page tables are sufficient. At this time, the format of the two-level page table is maintained by setting all the 页上级目录and bits to 0.页中间目录

During the memory initialization phase, the kernel must establish a physical address map to specify which physical address ranges are available to the kernel and which are not. The kernel marks the following page frames as reserved:

Page frames in unusable physical address ranges
Page frames containing kernel code and initialized data structures

Pages in reserved page frames must never be dynamically allocated or swapped to disk. The linear address space of a process is divided into two parts:

The linear address from 0x00000000 to 0xbfffffff can be addressed regardless of whether the thread is running in kernel mode or user mode
Linear addresses from 0xc0000000 to 0xffffffff can only be addressed by kernel-mode threads