Verilog Advanced Challenge 1 - Combination Logic Review + Introduction to Sequential Logic
foreword
- Hardware engineers have gradually become popular in recent years, and there are a lot of people who recruited into large factories with an annual salary of no less than 30-40w! And the number of big factories is not saturated!
- This issue is [Verilog Brush Questions] Hardware Engineer Advanced 1|Sequence Detection, if you don't understand anything, you can comment and discuss! - I recommend to everyone an artifact for writing questions and interviews . I also use this artifact to learn Verilog hardware code !
- ~The link is as follows: Brush the question interview artifact jump link
- You are also welcome to go to Nioke to view various information about hardware engineer recruitment positions, and conduct an early batch delivery interview!
- Novices can use this artifact to do daily quizzes, read the facebooks of big factories, learn basic computer knowledge, and communicate face-to-face with Daniels~ The pictures of the quizzes have been placed below~
Q1: Sequence detection where the input sequence is continuous
Problem description: Please write a sequence detection module to detect whether the input signal a satisfies the 01110001 sequence, and when the signal satisfies the sequence, an indication signal match is given.
The interface signal diagram of the
module is as follows: The timing diagram of the module is as follows:
Input description:
clk: system clock signal
rst_n: asynchronous reset signal, active low
a: single-bit signal, data to be detected
Output description:
match: When the input signal a satisfies the target sequence, the signal is 1, and the signal is 0 at other times
Case code:
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input a,
output reg match
);
parameter zero = 4'd0;
parameter one = 4'd1;
parameter two = 4'd2;
parameter three = 4'd3;
parameter four = 4'd4;
parameter five = 4'd5;
parameter six = 4'd6;
parameter seven = 4'd7;
parameter eight=4'd8;
reg [3:0] cu_st;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)begin
cu_st<=zero;
match<=1'b0;end
else begin
case(cu_st)
zero:if(a==1'b0)begin
cu_st<=one;
match<=1'b0;end
else begin
cu_st<=zero;
match<=1'b0; end
one:if(a==1'b1)begin
cu_st<=two;
match<=1'b0;end
else begin
cu_st<=one;
match<=1'b0; end
two:if(a==1'b1)begin
cu_st<=three;
match<=1'b0;end
else begin
cu_st<=one;
match<=1'b0; end
three:if(a==1'b1)begin
cu_st<=four;
match<=1'b0;end
else begin
cu_st<=one;
match<=1'b0; end
four:if(a==1'b0)begin
cu_st<=five;
match<=1'b0;end
else begin
cu_st<=zero;
match<=1'b0; end
five:if(a==1'b0)begin
cu_st<=six;
match<=1'b0;end
else begin
cu_st<=two;
match<=1'b0; end
six:if(a==1'b0)begin
cu_st<=seven;
match<=1'b0;end
else begin
cu_st<=two;
match<=1'b0; end
seven:if(a==1'b1)begin
cu_st<=eight;
match<=1'b0;end
else begin
cu_st<=one;
match<=1'b0; end
eight:if(a==1'b1)begin
cu_st<=three;
match<=1'b1;end
else begin
cu_st<=one;
match<=1'b1; end
default:begin cu_st<=zero;
match<=1'b0;end
endcase
end
end
endmodule
Q2: Sequence detection with extraneous terms
Problem description: Please write a sequence detection module to detect whether the input signal a meets the 011XXX110 sequence (the length is 9 bits of data, the first three are 011, the last three are 110, and the middle three are not required). When the signal meets the sequence , giving the indicator signal match.
The interface signal diagram of the
program is as follows: The function sequence diagram of the program is as follows:
Input description:
clk: system clock signal
rst_n: asynchronous reset signal, active low
a: single-bit signal, data to be detected
Output description:
match: When the input signal a satisfies the target sequence, the signal is 1, and the signal is 0 at other times
Case code:
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input a,
output reg match
);
reg [8:0] a_temp;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
a_temp<=9'b0;
else
a_temp<={
a_temp[7:0],a};
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
match<=1'b0;
else if(a_temp[8:6]==3'b011&&a_temp[2:0]==3'b110)
match<=1'b1;
else
match<=1'b0;
end
endmodule
Q3: Non-overlapping sequence detection
Description of the problem: Please write a sequence detection module to detect whether the input signal (a) meets the 011100 sequence. It is required to take every six inputs as a group, and do not detect repeated sequences. For example, if the first data does not match, the last five digits will not be considered. . The detection starts until the seventh bit of data, that is, the first bit of the next group of signals. When the signal satisfies the sequence, the indication signal match is given. When not satisfied, the indicator signal not_match is given.
The interface signal diagram of the
module is as follows: The timing diagram of the module is as follows:
Input description:
clk: system clock signal
rst_n: asynchronous reset signal, active low
a: single-bit signal, data to be detected
Output description:
match: When the input signal a meets the target sequence, the signal is 1, and the signal is 0 at other times
not_match: When the input signal a does not meet the target sequence, the signal is 1, and the signal is 0 at other times
Case code:
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
output reg match,
output reg not_match
);
reg [5:0]cs;
reg [5:0]ns;
reg [5:0]count;
always@(posedge clk or negedge rst_n)
if(!rst_n)
count<=0;
else if (count>=5)
count<=0;
else
count<=count+1;
always@(posedge clk or negedge rst_n)
if(!rst_n)begin
ns<=0;
cs<=0;
end
else
cs<=ns;
parameter IDLE=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6;
parameter NOT_MATCH=7;
always@(*)
case(cs)
IDLE:ns = (data==0)? s1:NOT_MATCH;
s1:ns = (data==1)? s2:NOT_MATCH;
s2:ns = (data==1)? s3:NOT_MATCH;
s3:ns = (data==1)? s4:NOT_MATCH;
s4:ns = (data==0)? s5:NOT_MATCH;
s5:ns = (data==0)? s6:NOT_MATCH;
s6:ns = (data==0)? s1:NOT_MATCH;
NOT_MATCH:ns = (data==0&&count == 5)? s1:NOT_MATCH;
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)begin
match<=0;
not_match<=0;
end
else if (count == 5)begin
if(ns==s6)begin
match<=1;
not_match<=0;
end
else begin
match<=0;
not_match<=1;
end
end
else begin
match <= 1'b0;
not_match <= 1'b0;
end
endmodule
Q4: Sequence detection for discontinuous input sequence
Problem description: Please write a sequence detection module, the input signal port is data, and the indicator signal port indicating that the data is valid is data_valid. When the data_valid signal is high, it means that the input signal data at this moment is valid and participates in the sequence detection; when the data_valid signal is low, the data is invalid, and the input at this moment is discarded. When the valid signal of the input sequence satisfies 0110, the sequence matching signal match is pulled high.
The interface signal diagram of the
module is as follows: The timing diagram of the module is as follows:
Input description:
clk: system clock signal
rst_n: asynchronous reset signal, active low
data: single-bit signal, data to be detected
data_valid: input signal valid flag, when the signal is 1, it means the input signal is valid
Output description:
match: When the input signal data satisfies the target sequence, the signal is 1, and the signal is 0 at other times
Case code:
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
input data_valid,
output reg match
);
parameter [3:0] data_ref = 4'b0110;
reg [3:0] data_in;
always @(posedge clk or negedge rst_n)
if(!rst_n) data_in <= 4'b0000;
else if(data_valid) data_in <= {
data_in[2:0],data};
always @(posedge clk or negedge rst_n) begin
if(!rst_n) match <= 1'b0;
else if((data_in[2:0] == 3'b011) && (!data)) match <= 1'b1;
else match <= 1'b0;
end
endmodule
Q5: Signal generator
Problem description: Please write a signal generator module to send out the corresponding waveform according to the waveform selection signal wave_choise: when wave_choice=0, send out a square wave signal; when wave_choice=1, send out a sawtooth wave signal; when wave_choice=2, send out a triangular wave signal.
The interface signal diagram of the
module is as follows: The timing diagram of the module is as follows:
Input description:
clk: system clock signal
rst_n: asynchronous reset signal, active low
wave_choise: 2-bit wide signal, output different waveform signals according to the value of the signal
Output description:
wave: 5-bit wide signal, output signals with different waveforms according to the value of wave_choise
Case code:
`timescale 1ns/1ns
module signal_generator(
input clk,
input rst_n,
input [1:0] wave_choise,
output reg [4:0]wave
);
reg [4:0] cnt;
reg k;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt <= 5'd0;
wave <= 5'd0;
end
else begin
case(wave_choise)
2'd0:begin
if(cnt == 5'd19) begin
cnt <= 5'd0;
wave <= 5'd0;
end
else if(cnt>=5'd9 && cnt<5'd19)begin
cnt <= cnt + 1'b1;
wave <= 5'd20;
end
else begin
cnt <= cnt + 1'b1;
wave <= 5'd00;
end
end
2'd1:begin
if(wave >= 5'd20)
wave <= 5'd0;
else
wave <= wave + 1'b1;
end
2'd2:begin
if(wave == 5'd0) begin
k <= 1'b0;
wave <= wave + 1'b1;
end
else if(wave == 5'd20) begin
k <= 1'b1;
wave <= wave - 1'b1;
end
else if(k == 1'b0 && wave < 5'd20)
wave <= wave + 1'b1;
else if(k == 1'b1 && wave > 5'd0)
wave <= wave - 1'b1;
else
wave <= wave - 1'b1;
end
default:begin wave <= wave;end
endcase
end
end
endmodule
Summary: The platform that Xiaobai and Daniel are using
- Hardware engineers have gradually become popular in recent years, and there are a lot of people who recruited into large factories with an annual salary of no less than 30-40w! And the number of big factories is not saturated!
- This issue is [Verilog Brush Questions] Hardware Engineers from 0 to Getting Started 3 | Combination Logic Review + Introduction to Sequential Logic, if you don't understand, you can comment and discuss!
Come and click on the link to jump and register, and start your nanny-level problem-solving road! The road of brushing questions and fighting monsters
In addition, there are not only questions here, but everything you want will be here, which is very suitable for beginners and beginners to learn~
1. Algorithms (398 questions): 100 questions must be brushed in the interview, introduction to algorithms, high-frequency interview list
2 , Data Structures (300 questions): All are very classic linked lists, trees, heaps, stacks, queues, dynamic programming, etc.
3. Languages (500 questions): C/C++, java, python introductory algorithm exercises
4, SQL (82 questions): Quick Start, SQL must know, SQL Advanced Challenge, Interview Question
5, Big Factory Written Exam Question: ByteDance, Meituan, Baidu, Tencent... Mastering experience is not afraid of interviews!
