Figure 14.1 Asynchronous Assertion - Problem Statement
So far in this book, we have always used the synchronous clock edge as the sampling edge for the assertion. There's a reason for this. The example presented here uses asynchronous edges (which are perfectly legal) as sampling edges. The problem statement becomes ''Whenever (i.e. asynchronously) L2TxData == L2ErrorData, L2Abort is asserted'. It seems very logical now, no need to use the clock. So, we write a property as shown in Figure 14.1. We simply say @(L2TxData) (i.e. whenever L2TxData changes) we compare L2TxData == L2ErrorData and if it matches we deduce L2Abort == 1.
Figure 14.1 (continued)
This sounds very logical. What's wrong with it? Hmm...a lot of stuff. The comments in Figure 14.1 systematically tell you what's going on. Please study it carefully to see why there is a problem. We will not repeat the explanation of this figure. But that's a high-level hint on the subject. "Sampling edge" (i.e. @(L2TxData)) is also used in comparison expressions. Since the value of the variable in the expression is always calculated in the presumed region, the L2TxData value in the expression will not be the same as when @(L2TxData) changes. If this sounds confusing, fine. That's why I don't recommend using async assertions.
Figure 14.2 Asynchronous Assertion - Problem Statement Analysis Continues
We continue the analysis in Figure 14.2. Comments explaining the reasons for frustration!
To avoid the problem we just described in Figure 14.3, we can (unfortunately) continue to sample edges asynchronously, it's just that we make all comparison expressions/variables part of the asynchronous sample edge. Solution 1 shows this, which will solve the problem we encountered the first time. Think about it and you'll see why.
Why did we assign #1 in solution 2? This way when L2TxData or L2Error DataW or L2ABortW changes, there is a delay of one unit time, which allows the new value to settle because you need to check (L2TxData == L2ErrorData).
This is a (puzzling) way to bypass the checks of these variables in the prediction region. If all of this seems confusing, don't be intimidated. I strongly recommend that you do not use async edges as sampling edges. Again, if you're comfortable using them, do so, but be careful. Please refer to the example above to help you understand the behavior of asynchronous sampling edges. Note that I've shown all three solutions with async assertions (very much against it!). How do you model this as a synchronous assertion? Please try to see if you succeed. Assume 'posedge clk' as your sampling edge.
Figure 14.3 Asynchronous assertion - solution
Solution 3 uses a program block to determine when you perform the check. Note that I am not using assertions in this solution. There are times when simply using Verilog is better and more intuitive and gives the results you expect. I recommend using pure Verilog for asynchronous assertion descriptions, and SVA for all other types of assertions.