I. Introduction
There are a lot of software involved in the RTL -level Asic design, and the author has not used every one of them. The Baidu cloud link of the software is given as follows, you can download it as needed. For the software harmony problem, please search on EETOP, or leave your mailbox; the latest userguide (2016 version) of the software is also available on EEOP.
Synopsy Software Baidu Cloud: https://pan.baidu.com/share/init?surl=T7zxs#list/path=%2F%E8%BD%AF%E4%BB%B6%2FSyn0psys.EDA.T00ls.2010 -2015.Collection-Password-0daydown&parentPath=%2F%E8%BD%AF%E4%BB%B6
Password: seq8
2. Tool introduction
RTL code rule checking tools: nlint , spyglass . These two software are mainly used to check the code for syntax and semantic errors, and can detect more problems than other tools, such as naming specifications, timing risks, power consumption, etc. For details, please refer to the software tutorial. nlint has Windows version and linux version. The Linux version of the software and the usage tutorial can be searched on eetop.
Rule checking tools are: ALTENTA: Spyglass; Synopsys: leda; NOVAS: nlint; Mentor: DesignChecker; Aldec: Active-HDL
RTL code simulation tools: There are many combinations of such simulation tools, such as: qustasim/modelsim , NC_verilog+Verdi, VCS+DVE, VCS+Verdi and so on. The combination I currently use is VCS+Verdi. These two softwares are the mainstream simulation software in the industry, and can also be simulated in combination with the UVM library. Of course, this is the content of the verification methodology.
Synthesis tool: Design Compiler . There is no one of the most commonly used synthesis tools. This software mainly "translates + optimizes + maps" the RTL code into a gate-level netlist corresponding to the process library. And also contains power analysis software Power Compiler and boundary scan register insertion software BSD Compiler.
Design for Testability: DFT Compiler + TetraMAX . The software is used after DC , DFT Compiler is used to replace the internal registers of the design with scan registers and form one or more scan chains, and TetraMAX is used to automatically generate test vectors.
Formal verification tools: Formality , Conforml (produced by candence). The equivalence verification tool is mainly used for verification after DFT Compiler inserts the scan chain. In addition, after synthesizing the clock tree in the layout and inserting the BUFFER, this tool also needs to be used for equivalence verification.
Static Timing Analysis Tool: Prime Time . One of the most commonly used timing analysis tools in the industry, this software includes the power analysis PTPX tool, which is a must for power analysis. Cadence also has a corresponding timing analysis tool - Encounter Timing System.
Automatic place and route tool (APR ): ICC , Enconter . Which Encounter is Cadence company.
Digital-analog hybrid simulation: nanosim + VCS , the upgraded version of nanosim is XA.
This is an introduction to the synopsys EDA tool software, I hope it will be helpful to partners who are not clear about the use of EDA software. http://bbs.eetop.cn/thread-151171-1-1.html
3. Book Recommendations
"Verilog HDL Hardware Description Language"
"Design and Verify Verilog HDL "
"Verilog Code Style Specification for Enterprise"
"Verilog Language Coding Style"
"VerilogHDL Code Style Specification"
"Verilog HDL Advanced Digital Design"
"Soc Design Method and Implementation"
"Advanced ASIC Chip Synthesis"
"Huawei Verilog Typical Circuit Design"
"Digital IC System Design"
"Digital Integrated Circuits-- Circuits, Systems and Design"
"A Practical Tutorial on Application-Specific Integrated Circuit Design"
"Integrated Circuit Static Timing Analysis and Modeling"
"CMOS integrated circuit back-end design and actual combat"
"makefile tutorial"
"Brother Bird's Private Kitchen"
"SystemVerilog and Functional Verification"
"UVM combat"
"Communication IC Design (Volume 1 and 2)"
"Digital Image Processing and Image Communication"
"FPGA Implementation of Digital Signal Processing Chinese Version"
Various types of Synopsy userguide , EETOP has a 16-year version.
3. Description of the process library
Using DC, PT, FM, ICC or ENCOUNTER software requires process library files, mainly including digital logic unit files, symbol library, synthesis library, parasitic capacitance parameter library, layout file LEF, milkway library and so on.
The library of SMIC180 can be found on EETOP. http://bbs.eetop.cn/thread-611843-1-1.html . Regarding the function of each folder of the craft library, the author will introduce it in detail in the chapter of "Technical Library Description". If there are any omissions, please bear with me.