module D_flip_flop(
input [1:0] d,
input clk,
output reg[1:0] q,
output reg[1:0] qb
);
always @(posedge clk) // The rising edge of the clock triggers the D flip- flop
begin
q<= d ;
qb<= ~d ;
end
endmodule
2. RS trigger
module SY_RS_FF ( R, S, CLK, Q, QB ); //Module name and parameter definition, the range is endmodule.
input R, S, CLK; //input port definition
output Q, QB; //output port definition
reg Q; //register definition
assign QB = ~Q; //assign statement, QB=/Q.
always @( posedge CLK ) //On the rising edge of CLK, execute the following statement.
case ({ R ,S }) //case statement, as far as endcase.
1:Q <= 1; //When the combination of R and S is 01, let Q=1.
2:Q <= 0; //When the combination of R and S is 01, let Q=1.
3:Q <= 1'bx; //When the combination of R and S is 11, let Q be a 1-bit number, and the value is indeterminate (x).
endcase //case statement ends
endmodule //end of module
3. JK flip-flop
module JK(clk,j,k,q,r,s,seg); input clk,j,k,r,s; output q;
output [7:0]seg; reg q=0; reg [7:0]seg;
always @(posedge clk)
begin
if(r==1 && s==0)
begin
q<=0;
end
if(r==0 && s==1)
begin
q<=1;
end
if(r==0 && s==0)
begin
if(j==1 && k==1)
begin
q<=~q;
end
if(j==1 && k==0)
begin q<=1;
end
if(j==0 && k==0)
begin
q<=q;
endif(j==0 && k==1)
begin q<=0;
end
end
end
endmoudle
4.T flip-flop
input T,
input clk,
output Q,
output QB,
always@(posedge clk)
begin
if(~reset)
begin
Q<=1'b0;
end
else
begin
if(T)
Q<=~Q;
QB<=~Q;
else
begin
Q<=Q;
QB<=~Q;
end
end
end