1. The master device sends data to the slave device.
The master device sends a start bit, which will notify all devices on the bus that the transmission has started, and then the host sends the device address. The slave that matches this address will continue the transfer process, and Other slaves will ignore the next transfer and wait for the next transfer to start. After the master device addresses the slave device, it sends the internal register address of the slave device it wants to read or write; after that, it sends the data. After the data is sent, the stop bit is sent: the
writing process is as follows:
~Send start bit
~Send the address and read/write selection bit of the slave device; release the bus, wait until the EEPROM pulls the bus low to respond; if the EEPROM receives successfully, it responds; if there is no successful handshake or the sent data is wrong, the EEPROM does not respond, this Retransmission or termination is required.
~ Send the internal register address you want to write; EEPROM responds to it;
~send data
~Send stop bits.
~After the EEPROM receives the stop signal, it enters an internal write cycle, which takes about 10ms, during which any operation will not be responded by the EEPROM; (so a delay must be inserted between two writes in this way, Otherwise it will fail)
2. The process of the master reading data:
the reading process is more complicated. Before reading data from the slave, you must first tell it which internal register you want to read, so you must first write it (dummy write):
~Send slave address+write bit set;
~send internal register address;
~Resend the start bit, ie restart;
~Resend slave address + read bit set;
~ read data
~The host receiver will also not send an ACK signal after the last byte has been received. The slave transmitter then releases the SDA line to allow the master to signal a P to end the transfer.
~ send stop bit
3. Cause analysis of bus deadlock
I2C总线写操作过程中，主机在产生启动信号后控制SCL产生8个时钟脉冲，然后拉低SCL信号为低电平，在这个时候，从机输出应答信号，将SDA信号拉为低电平。如果这个时候主机异常复位，SCL就会被释放为高电平。此时，如果从机没有复位，就会继续I2C的应答，将SDA一直拉为低电平，直到SCL变为低电平，才会结束应答信号。而对于主机来说，复位后检测SCL和SDA信号，如果发现SDA信号为低电平，则会认为I2C总线被占用，会一直等待SCL和SDA信号变为高电平。这样，主机等待从机释放SDA信号，而同时从机又在等待主机将SCL信号拉低以释放应答信号，两者相互等待，I2C总线进人一种死锁状态。同样，当I2C进行读操作时，从机应答后输出数据，如果在这个时刻主机异常复位而此时从机输出的数据位正好为0，也会导致I2C总线进入死锁状态。
参考博客：
http://blog.csdn.net/firefly_cjd/article/details/51921129
http://www.cnblogs.com/BitArt/archive/2013/05/28/3103917.html