The difference between variable (variable) and signal (signal) in vhdl

 Signal (signal) variable (variable)
assignment: <= : =

Definition: in structure in process

Scope of application: global in a process

Delay: yes no

Assignment: Immediately assign a value at the end of the process

A few things to note:

1. The variable is assigned at the end of the process, so if you assign multiple times in the process, only the last one is taken.

2. Because fpga is processed in parallel by a process, a variable can only be assigned in one process, otherwise an error will occur.