8K video processing and working principle, 8K video processing analysis

      With the continuous development of video technology, the resolution has developed from 480P to 1080P; when we have not fully realized that 4K TV will dominate the world, the live broadcast of has already begun. video requires about 33M pixels of data to be processed per frame. Massive data processing brings a very big challenge to the current video processing system. In the current field of large-screen wall construction, the current video processing platforms cannot meet the requirements of all aspects from video acquisition to

    The 8K standard was established a few years ago, and 8K video sources have gradually emerged since then. On August 23, 2012, the International Telecommunication Union (ITU), a subsidiary of the United Nations, adopted the 7680x4320 resolution [2] recommended by Japan's NHK TV as the international 8K ultra-high-definition TV (Super Hi-Vision-SHV). ) standard; in 2013, Japan's NHK produced the film "Delicious Delicious Food", which was shot, produced and projected in 8K resolution (7680×4320), with a resolution of 16 times that of 1080p, and 8K video (24fps) without compression. ) can reach 1GB per second; in 2015, NHK used 8K technology to live broadcast the Women's World Cup in Canada; on August 5, 2016, the 31st Summer Olympics were held in Rio de Janeiro, Brazil, and 8K live broadcast was a bright spot.

    With the establishment of the standard, the development of 8K cameras is also very rapid. In 2012, the Super Hi-Vision video capture camera launched by NHK was larger in size; the Super Hi-Vision video capture camera after 2013 was much smaller and more portable. The Sony F65RS is an 8K camera currently on the market. Panavision officially released the DXL in June 2016. The Panavision DXL claims to be the most complete camera system, with a 35.5-megapixel 8K CMOS sensor that can record 8K video at up to 60 fps


     The image effect brought by 8K is very realistic, and it can bring a sense of fineness beyond the quality of traditional radio and television. However, in terms of 8K video processing, there is a big problem because of its huge amount of data. Taking 24 frames of 8K video as an example, if the color depth of each bit reaches 6 bits, the data bandwidth for processing a single channel of 8K needs to be as high as 14.3Gbps.

   8K video processing system structure and working principle

   

       The difficulty of the 8K video processing system mainly lies in the bandwidth. Therefore, based on the current chip processing level, the main idea of ​​designing the processing system is to segment the video. One channel of 8K video, finally through the video processor, output 16 channels of 1080p video. The working principle is mainly to convert the code stream into 4 channels of HDMI2.0 output through Socionext's 8K decoding chip, and the 4 channels of HDMI2.0 are finally decomposed into 16 channels of 1080p video for display on the splicing wall. The specific video processing block diagram is shown in Figure 2. Each HDMI2.0 is equivalent to a 4K video, and 8K is equivalent to a combination of 4 4K videos. After the HDMI2.0 stream comes out, the high-speed FPGA chip decodes the HDMI2.0, and decomposes each HDMI2.0 signal into 4 channels of 1080p video streams, which is convenient for subsequent high-speed signal transmission and processing. In the high-speed logic chip, the data of 2 channels of 1080P video is serialized and transmitted, and the rate of each pair of serdes is up to 6.25Gbps. For the special application of large-screen splicing, each pair of high-speed serdes also enters a high-speed crossover module. The main function of this module is to schedule video signals, similar to the matrix function, to meet the needs of splicing display. After the serialized video reaches the back-end FPGA chip through the transmission path, deserialization is performed in the chip. At the same time, video processing is performed in the logic in 1080p units, including overlay, scaling, image enhancement, and rotation. Output to TMDS encoding chip SII1164. Finally, the sII1164 outputs video in the form of DVI.

  In a specific processor system, the functional modules in Figure 2 will be divided into several sections to complete, namely 8K signal acquisition board, high-speed signal exchange board and signal output processing board. Among them, the 8K signal acquisition board completes the decoding, segmentation and serdes sending functions of the 8K signal, the switching board completes the cross-distribution function of the high-speed signal, and the signal output processing board completes the signal deserialization, video processing and output functions.

    

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