Original blog address:
https://blog.csdn.net/jax_lee/article/details/6764471
http://www.52rd.com/Blog/Detail_RD.Blog_zx_zx_13124.html
10110101 can be seen as 2^7+2^5+2^4+2^2+2^0,
When using CRC check, the sender and receiver use the same generator polynomial g(x), and the coefficient of the sum bit and the last bit must be 1
The CRC processing method is:
the sender removes t(x) by g(x), and obtains the remainder as the CRC check code.
During verification, it is determined whether the data frame is in error based on whether the calculated correction result is 0.
The CRC check can detect 100% of all odd random errors and burst errors of length less than or equal to k (k is the order of g(x)).
Therefore, the higher the order of the generator polynomial of the CRC, the smaller the probability of misjudgment.
CCITT recommends: 2048kbit/s PCM base equipment adopts CRC-4 scheme, and the CRC check used adopts 16-bit CRC check.
In the Frame Check Sequence FCS of IBM's Synchronous Data Link Control Protocol SDLC, CRC-16 is used.
The higher the number of bits of g(x), the stronger the error detection ability.
Due to the reliability of CRC-32, it is very suitable to use CRC-32 for important data transmission, so it is widely used in communications, computers and other fields.
In some UART communication control chips (such as MC6582, Intel8273 and Z80-SIO), CRC check code is used for error control; in
Ethernet card chips and MPEG decoding chips, CRC-32 is also used for error control.
The basic idea of the CRC check code is to use the linear coding theory, and at the sending end, according to the k-bit binary code sequence to be transmitted, a monitoring code (ie, CRC code) r bits for checking is generated according to certain rules,
and attached to the information. After that, a new binary code sequence number of (k+r) bits is formed, and finally sent out.
At the receiving end, it is checked according to the rules followed between the information code and the CRC code to determine whether there is an error in the transmission.
In the field of data storage and data communication, CRC is everywhere: the FCS (Frame Error Detection Sequence) of the famous communication protocol X.25 uses CRC. CCITT, ARJ, LHA and other compression tool software use CRC32. CRC16 is used for reading and writing.
Common image storage formats such as GIF and TIFF also use CRC as an error detection method.
The essence of CRC is the remainder of modulo-2 division, and the type of CRC is different depending on the divisor used.
Usually, the divisor of the CRC is represented by a generator polynomial. The most commonly used CRC code generator polynomials are CRC16, CRC32.
Taking CRC16 as an example, the rule for generating a 16-bit CRC code is to first shift the binary sequence number to be sent left by 16 bits (that is, multiply by 2^16), and
then divide it by a polynomial. The final remainder is both the CRC code, As shown in the following formula,
where K(X) represents the binary sequence number of n bits, G(X) is a polynomial, Q(X) is an integer, and R(X) is the remainder (ie, CRC code).
K(X)>>16=G(x)Q(x)+R(x)
The modulo 2 addition and subtraction algorithm used to find the CRC code is a bitwise addition and subtraction without carry and borrow. This addition and subtraction operation is actually a logical XOR operation.
Addition and subtraction are equivalent, multiplication and division. The operations are the same as the multiplication and division operations of ordinary algebraic expressions, and conform to the same rules.
The polynomial for generating the CRC code is as follows, where CRC-16 and CRC-CCITT generate a 16-bit CRC code, while CRC-32 generates a 32-bit CRC code
The receiver divides the received binary sequence number (including the information code and CRC code) by the polynomial. If the remainder is 0, it means that there is no error in the transmission, otherwise it means that the transmission is wrong. The principle will not be described here. When the CRC code is calculated by software, the receiver can obtain the CRC code from the received information code, and check whether the comparison result is the same as the received CRC code.
In the frame check sequence FCS of the advanced data link control procedure HDLC recommended by CCITT, CCITT-16 or CRC16 is used, and its generator polynomial is G(x)=x16+x12+x5+1, and the generator polynomial of CRC-32 is G (x)=x32+x26+x23+x22+x16+x11+x10+x16+x8+x7+x5+x4+x2+x+1
Algorithm Analysis of CRC Check Code
The encoding method of the CRC check code is to divide the binary data t(x) to be sent by the generator polynomial g(x), and use the final remainder as the CRC check code.
The implementation steps are as follows:
the data block to be sent is assumed to be an m-bit binary polynomial t(x), and the generator polynomial is g(x) of order r.
Add r zeros at the end of the data block, the length of the data block is increased to m+r bits, and the corresponding binary polynomial is .
Remove it with the generator polynomial g(x), and find the remainder as a binary polynomial y(x) of order r-1.
This binary polynomial y(x) is the CRC check code encoded by the generator polynomial g(x) of t(x).
Subtract y(x) in a modulo 2 manner to obtain a binary polynomial, which is the string to be sent containing the CRC check code.
It can be seen from the coding rules of CRC that CRC coding actually converts the m-bit binary polynomial t(x) sent on behalf of it into an m+r-bit binary polynomial that can be divided by g(x),
so it can be used for decoding. The received data is removed by g(x). If the remainder is zero, it means that there is no error in the transmission process;
if the remainder is not zero, there must be an error in the transmission process.
Many CRC hardware decoding circuits perform error detection in this way.
At the same time, it can be regarded as a combination of t(x) and CRC check code, so when decoding, the received binary data is removed from the r-bit data at the tail, and the original data is obtained.
In order to understand the encoding process of the CRC check code more clearly, a simple example is used to illustrate the encoding process of the CRC check code.
Since the encoding process of CRC-32, CRC-16, CCITT and CRC-4 is basically the same, only the number of bits and the generator polynomial are different.
Name generator polynomial abbreviation * The standard refers to
CRC-4 x4+x+1 3 ITU G.704
to get: the order r is 4, that is, 10011
In order to simplify the description, an example of CRC-4 encoding is used to illustrate the encoding process of CRC .
Let the data to be sent t(x) be 12-bit binary data 100100011100; the generator polynomial of CRC-4 is g(x) = , and the order r is 4, that is, 10011.
First, add 4 0s at the end of t(x), and the data block becomes 1001000111000000.
Then remove it with g(x), no matter what the quotient is, just ask for the remainder y(x). The table below shows the division process.
XOR operation, same as 0, different as 1
As can be seen from the above table, CRC encoding is actually a cyclic shift modulo 2 operation.
For CRC-4, we assume that there is a 5bits register, and through repeated shifting and CRC division,
the final value in the register after removing the highest bit is the remainder we require.
So the above steps can be described by the following process:
//reg is a 5-bit
register . Set the value in reg to 0.
Add r 0s to the original data.
While (the data is not processed)
Begin
If (reg first is 1)
reg = reg XOR 0011.
Put reg The value in is shifted one bit to the left, and a new data is read and placed in the 0 bit position of the register.
The last four digits of End
reg are the remainder we require.
This algorithm is simple and easy to implement, and is applicable to G(x) generator polynomials of any length.
It can be used when the data to be sent is not too long. But if the data block sent is very long, this method is not suitable.
It can only process one bit of data at a time, which is too inefficient.
In order to improve processing efficiency, 4-bit, 8-bit, 16-bit, and 32-bit can be processed at a time.
Since the structure of the processor basically supports the processing of 8-bit data, it is more appropriate to process 8 bits at a time.
In order to have an intuitive understanding of the optimized algorithm, first understand the above algorithm from another angle.
In the above example, the encoding process can be seen as the following process:
Since only the remainder is needed at the end, we only look at the last four bits.
Construct a four-bit register reg, the initial value is 0, the data is shifted into reg0 (0 bit of reg) in turn, and the data of reg3 is shifted out of reg.
With the above algorithm, we can know that only when the shifted data is 1, reg performs XOR operation with g(x);
when the shifted data is 0, reg does not perform XOR operation with g(x), which is equivalent to performing XOR operation with 0000. XOR operation.
That is to say, reg and what kind of data are XORed out to determine the data.
Since there is only one bit, there is a choice. The above algorithm can be described as follows,
//reg is a 4-bit register
Initialize t[]={0011,0000}
and set the value in reg to 0.
Add r 0s after the original data.
While (the data is not processed)
Begin
shifts the value in reg one bit to the left, reads a new data and places it at the 0 bit position of register.
reg = reg XOR t[shifted bits]
End The
above algorithm is processed in bits, and the above algorithm can be extended to 8 bits, that is, processed in Bytes, that is, CRC-32.
Construct a register reg with four bytes, the initial value is 0x00000000, the data is moved into reg0 in turn (the 0 byte of reg, similar to the following), and the data of reg3 is moved out of reg.
By analogy with the above algorithm, it can be seen that the data bytes that are shifted out determine what kind of data reg is XORed with.
Since there are 8 bits, there is a choice. The above algorithm can be described as follows:
//reg is a 4 Byte register
Initialize t[]={…}//Total=256 items
Set the value in reg to 0.
Add r/8 0 bytes to the original data .
While (unfinished data)
Begin
shifts the value in reg one byte to the left, reads a new byte and places it at the 0th byte position of reg.
reg = reg XOR t[shifted bytes] The basis of the
End
algorithm is related to the property of polynomial division.
If an m-bit polynomial t(x) is divided by a generator polynomial g(x) of order r,
each bit (0=