Program query method:
Once the CPU starts I/O, it must stop the running of the current program and insert a program into the current program.
The CPU has a "step" waiting phenomenon, and the CPU and I/O work serially
Advantages: Simple interface design, less equipment
Disadvantages: The CPU spends a lot of time in the process of information transmission for querying and waiting, and can only exchange information with one peripheral within a period of time, which greatly reduces the efficiency.
Only one word can be transferred at a time: the data from the peripheral is placed in the CPU's registers. That is, every time a word is transmitted, the CPU has to query it once. So, using the program query method is very slow
Program interruption method:
The interrupt service routine is also a program, which is executed by the CPU, so it involves program switching, so it is necessary to protect the scene and restore the scene
DMA mode:
Every time a piece of data is ready, the CPU is interrupted, and the CPU runs the interrupt service routine to complete a transfer.
High-speed devices require large batches of data transfers -> a lot of CPU time for interrupt servicing.
DMA controller : There is a DMA controller on the DMA bus, and the hardware realizes the control of large batch data transmission
In the DMA mode, when the I/O device needs to perform data transfer, a DMA transfer request is made to the CPU through the DMA controller (DMA interface) , and the
CPU will give up the system bus after responding, and the DMA controller will take over the bus for data transfer.
Its main functions are:
1) Accept the peripheral DMA request, and issue a bus request to the CPU.
2) The CPU responds to the bus request, issues a bus response signal, takes over the bus control, and enters the DMA operation cycle.
3) Determine the address and length of the main memory unit of the transmission data, and can automatically modify the main memory address count and transmission length count.
4) Specify the transfer direction of data between the main memory and peripherals, issue control signals such as read and write, and perform data transfer operations.
5) Report the end of the DMA operation to the CPU.
The CPU only needs preprocessing and postprocessing
Conflicts can occur when an I/O device and the CPU access main memory at the same time. solve:
(1) Stop CPU access to main memory
Insufficient utilization of CPU to main memory
(2) DMA and CPU alternate memory access
Complex hardware logic
(3) Cycle appropriation (cycle stealing)
There are three possibilities for DMA access to main memory:
CPU is not accessing memory at this time (no conflict)
CPU is accessing memory (the end of the access cycle gives up the bus)
CPU and DMA request memory access at the same time (I/0 memory access priority)
