1. Count the number of memory chips
1. The following example: Note that the calculation unit of memory capacity is KB, and the memory chip capacity is bit
The concept of overflow
1. If the computer uses double sign bits, when two numbers with the same sign are added, when the two sign bits are 1 after the logical XOR operation, it can be judged that the result of the addition of these two numbers has overflowed.
2. When the sign bit of the result is 01, it is called overflow
3. When the sign bit of the result is 10, it is called underflow
3. Representation of the number of machines
1. The data in the computer is divided into two kinds of representation: fixed-point number and floating-point number
(1) Floating-point number representation uses exponents and mantissas to represent numbers, called floating-point numbers
(2) In the case of the same total number of digits, floating-point numbers can represent larger numbers
(3) The numbers represented by fixed-point numbers are divided into fixed-point integers and fixed-point decimals
(4) Fixed-point number means that the decimal point position of all numbers in the computer is fixed by artificial convention, so the decimal point does not need to occupy the storage position
4. IR instruction register
1. The number of bits in the instruction register (IR) depends on the instruction word length
2. The instruction register (IR) stores an instruction currently being executed from the main memory alone
3. When the instruction register (IR) executes an instruction, it is first fetched from the memory to the data register (DR), and then transferred to the IR
4. Instructions are divided into opcode and address code fields, which are composed of binary digits, so the number of bits in the instruction register (IR) depends on the instruction word length
5. Controller
1. The role of the controller: not only to ensure the correct execution of instructions, but also to be able to handle abnormal events
2. The central controller (CPU) is the operation and control core of a computer, and its function is to interpret computer instructions and process data in computer software
3. The central controller (CPU) consists of operators, controllers and registers, as well as a bus that realizes the data, control and status of the connection between them
4. Operator: complete arithmetic operations, logical operations and shift operations
5. Controller: realize the orderly sending of control signals in the process of reading, registering, decoding and execution of the like, mainly responsible for decoding the instructions, and issuing the control of each operation to be performed to complete each instruction Signal
6. Register: used to temporarily store information during addressing and calculation
Six, virtual memory (Virtual Memory)
1. Virtual Memory: In a computer system with a hierarchical memory, the functions of partial loading and partial replacement are automatically realized, which can logically provide users with an addressable "addressable" memory that is much larger than the physical storage capacity. main memory".
2. The capacity of the virtual storage area has nothing to do with the size of the physical main memory, but is limited by the address structure of the computer and the available disk capacity.
3. According to the memory mapping algorithm used, there are mainly three types of virtual memory management methods: segment type, page type, and segment page type.
4. Common virtual memory (Virtual Memory) consists of main memory - auxiliary memory two-level memory plus auxiliary software and hardware
Seven, Cache (cache memory)
1. About cache: We all know that the speed of CPU processing data is very fast. Although the read and write speed of memory is not slow, it is too slow compared to CPU, so if we simply let CPU read and write memory , most of the time consumed is in the processing of data in the memory, and at this time the CPU is waiting idle, wasting resources, so it is necessary to connect a Cache between the CPU and the memory as a buffer.
2. Basic features: Since Cache appears to alleviate the slow processing of data in memory, a basic feature that Cache should have is that it can read and write data quickly, can better match the speed of the CPU, and keep the CPU busy as much as possible. However, because of its fast processing speed, its capacity is relatively small. If it can be both large in capacity and fast in speed, it would be good to directly increase the speed of the memory to match the speed of the CPU, but due to the material Due to the price, technical complexity and other reasons, Cache is still very necessary.
3. Basic structure: The basic storage unit of the Cache memory bank is a block, and each block has an intra-block address, and the Cache address is represented by a block number and an intra-block address. In addition to the block, there are tags. The tags are used to identify the wrongly wanted data in the Cache at this time. If there are tags, the Cache is processed directly. If the tags are not found, the data is transferred to the main memory. There are also several mechanisms in the Cache, the replacement mechanism and the address mapping conversion mechanism.
4. During program execution, the address mapping of Cache (cache) and main memory is automatically completed by hardware
5. The storage architecture is: Cache (cache memory) - main memory - auxiliary memory, three levels, the role of address mapping is to convert the main memory address sent by the CPU into the address of the Cache (cache memory)
6. Address mapping: The block of main memory is copied to the Cache (cache memory) according to certain rules. The image can be divided into:
(1) Fully associative image
(2) Direct image
(3) Group associative image
7. Cache (cache memory) has a special replacement algorithm. The mapping of Cache (cache memory) and the main memory address is automatically completed by hardware, and it mainly stores a copy of part of the main memory data.
Eight, associative memory
1. Associative memory is a content-addressable memory. The working principle is to use data and a part of the data as a key, compare the key with each unit in the memory, and find out all the keys in the memory that are related to the key. same setup
2. Composition: compare register, mask register, word selection register, search result register, etc.
CR compare register: store the number to be compared (retrieved content).
MR mask register: When searching according to the partial content of the comparison number, correspondingly set the bit to be compared in MR to "1", and set the bit not to be compared to "0". Fields set to "1" are key fields.
SRR search result register: If the i-th word of the comparison result meets the requirements, the i-th bit is set to "1", and the rest are "0".
WSR word selection register: determine which words participate in the retrieval, and the corresponding bit is "1" if it participates in the retrieval.
9. Main memory
1. Main memory is referred to as main memory: used to store instructions and data, which is directly accessed randomly by the CPU
2. Main memory composition:
(1) Memory Bank
(2) Control circuit
(3) Address register
(4) Data register
(5) Address decoder
3. Addressing system: The addressing system is composed of the address register, the address decoding circuit and the driver. The address determined by the CPU is first sent to the address register, and then the storage unit to be accessed is found according to the decoding circuit. The function of the driver between the decoders is to reduce the drive load capacity of the decoding line
10. Interruption
1. The essence of an interrupt is a real-time controlled interface that the processor opens to the outside world.
An uninterrupted computer system is deterministic: knowing all the data states of the CPU and memory at a certain moment, it is possible to deduce all future processes. Such a computer cannot interact, just an accelerator. When interrupts are added, the computer specifies which external commands are compatible and sets up service routines that may interrupt the current task. This makes the CPU "executing program" and "service that may occur at any time", the two form an asynchronous relationship, and the introduction of external input makes computer programs no longer deterministic. Interrupt inputs, controlled by humans in real time, are unpredictable. By regularizing and promoting interrupt response, non-computer science people can control computers and be creative. Gaming mouse micro-manipulation, digital board drawing, audio input synthesis, post-image value adjustment, keyboard commenting on the world trend, these are not fixed processes, but events that require people to create and participate in real-time, using interruption as a carrier and combining with computers up. Interrupts are the standard input interface of the processor. As far as the hardware details are not that important, it depends on the instruction specification. You can directly pull the external pins to the CPU Retire unit; you can also build an interrupt controller to coordinate the reception of external signals and then forward them. Both are available on x86. The latter is sent from the south bridge to the IO APIC and then to the core APIC and then to the Retire unit. The CPU also has a certain degree of freedom and will respond at the appropriate time.
2. The interrupt vector can provide the entry address of the interrupt service routine, and the location of the interrupt vector stores a jump instruction that jumps to the entry address of the interrupt service routine
3. Interrupt vector: the interrupt identification code generated by the hardware (the identification mark of the interrupt source, which can be used to form the entry address of the corresponding interrupt service routine or store the first address of the interrupt service routine)
11. DMA
1. DMA overview: The English spelling of DMA is "Direct Memory Access", which means direct memory access in Chinese. DMA can refer not only to the computer technology of memory access, which is the direct access of data by memory and peripherals, but also to the hardware module that implements this technology (for a general-purpose computer PC, the DMA control logic consists of a CPU and a DMA control interface logic chip). , The DMA controller of the embedded system is built in the processor chip, generally called the DMA controller, DMAC).
2. DMA memory access technology: The advantage of using DMA is that it does not require the intervention of the CPU and directly serves the peripherals, so that the CPU can handle other transactions, thereby improving the efficiency of the system. For slow devices, such as UART, its role It only reduces the CPU usage, but for high-speed devices, such as hard disks, it not only reduces the CPU usage, but also greatly improves the throughput of hardware devices. Because for such a device, the speed at which the CPU directly supplies data is too slow. Because the CPU can only access the bus at most once per bus cycle, and for ARM, it cannot directly move the value of the A address in the memory to the B address. It can only move the value of the A address to a register first, and then move from this register to the B address. That is, for ARM, it takes two bus cycles to get the value of the A address to the B address. The DMA is different. The DMA in the general system has the capability of burst transmission. In this mode, the DMA can transmit several or even dozens of bytes of data at a time, so the use of DMA can make the device Throughput capacity is greatly enhanced.
3. When using DMA, we must pay attention to the following facts: DMA uses physical addresses, and programs use virtual addresses, so virtual addresses must be converted into physical addresses when configuring DMA.
Because the program uses virtual addresses, and generally uses cache addresses, the content in the cache may not be consistent with the content of its physical address (memory), so the cache of the address must be refreshed before starting the DMA transfer, that is, written to the memory.
The OS does not guarantee that the memory space allocated each time is physically contiguous. Especially when the system has been used for a period of time and a relatively large memory is allocated. So every time you need to judge whether the address is continuous, if not, you need to divide this memory into several segments to let DMA complete the transfer
4. The basic configuration of DMAC: DMA is used directly by the dedicated controller without CPU intervention (DMA controller) to create an application for source and destination transfers, thus freeing up the CPU for bulk data transfers. DMA in PIC32 microcontrollers can be used to map to different peripherals in the memory space like from memory areas to devices like SPI, UART or I2C. Please refer to the device reference manual for the DMA features. Here is only a brief analysis of some basic principles and functions.
Address register Stores the address of the storage unit during DMA transfer
Byte counter Stores the number of bytes transferred by DMA
Control register Stores the DMA transfer mode set by the CPU, control commands and other
status registers store the current state of the DMAC, including whether there is a DMA request and whether it is finished Etc.
5. Independent DMA control chip
In the course "Microcomputer Principles", we will talk about an independent DMA control chip 8237A under X86. The tasks of each channel of the 8237A control chip in the PC:
CH0: Refresh control used as dynamic memory
CH1: Reserved for users
CH2: DMA control for floppy disk drive data transfer
CH3: DMA control for hard disk drive data transfer
6. DMA in embedded devices: direct memory access (DMA ) controller is a unique peripheral that transfers data within the system and can be thought of as a controller capable of connecting internal and external memory to each DMA capable peripheral via a set of dedicated buses. It is a peripheral because it performs the transfer under the programmed control of the processor. It is worth noting that usually only peripherals with large data traffic (kBps or higher) need to support DMA capability. Typical examples of these applications include video, audio and network interfaces.
7. The DMA controller will include an address bus, a data bus and control registers. An efficient DMA controller will have the ability to access any resource it needs without the intervention of the processor itself, which must be able to generate interrupts. Finally, it must be able to calculate the address inside the controller.
8. A processor can contain multiple DMA controllers. Each controller has multiple DMA channels and multiple buses that connect directly to memory banks and peripherals, as shown in Figure 1. Two types of DMA controllers are integrated in many high-performance processors. The first type is often called "system DMA controller" and can implement access to any resource (peripherals and memory). For this type of controller, the number of signal cycles is counted in the system clock (SCLK). , Take ADI's Blackfin processor as an example, the frequency can reach up to 133MHz. The second category is called the Internal Memory DMA Controller (IMDMA), which is dedicated to inter-access operations between internal memory locations. Because the access takes place internally (L1-L1, L1-L2, or L2-L2), the number of cycles is counted based on the core clock (CCLK), which can exceed 600MHz.
9. Each DMA controller has a set of FIFOs that act as buffers between the DMA subsystem and peripherals or memory. For MemDMA (Memory DMA), there is a set of FIFOs at the source and destination of the transfer. When resources are tight and data transmission cannot be completed, FIFO can provide a temporary storage area for data, thereby improving performance.
10. Because the DMA controller is usually configured during code initialization, the core only needs to respond to the interrupt after the data transfer is complete. You can program the DMA control to move data in parallel with the core, while at the same time letting the core perform its basic processing tasks—work it should focus on getting done.
11. DMA settings: There are two main types of DMA transfer structures: register mode and descriptor mode. Regardless of the type of DMA, the types of information described in Table 1 will appear in the DMA controller. When the DMA operates in register mode, the DMA controller simply uses the parameter values stored in the registers. In descriptor mode, the DMA controller looks up its own configuration parameters in memory.
12. Register-based DMA: Inside the register-based DMA, the processor directly programs the DMA control registers to initiate transfers. Register-based DMA provides the best DMA controller performance because registers do not need to constantly load data from descriptors in memory, and the kernel does not need to maintain descriptors.
13. Register-based DMA consists of two sub-modes: Autobuffer mode and Stop mode. In automatic buffered DMA, when a transfer block is completed, the control register is automatically reloaded with its original set value, and the same DMA process is restarted with zero overhead.
14. In the DMA working mode, a direct data channel is established between the main memory and the peripherals
12. Register addressing and immediate addressing
example:
Thirteen, class inheritance
1. Through class inheritance, the code of the base class can be reused in the program
2. New code can be added to the inherited class
3. In the inherited class, a method with the same name as the method in the inherited class (base class) can be defined
4. The methods in the inherited class (base class) can be overridden in the inherited class
14. Software Development Model
1. The advantages and disadvantages of the software development model.
Advantages of the waterfall model:
1) Provides checkpoints for the project by stages.
2) After the previous stage is completed, you only need to focus on the subsequent stage.
3) The waterfall model can be applied in an iterative model.
Disadvantages of waterfall model:
1) There is very little feedback between the various stages of the project.
2) Results can only be seen later in the project life cycle.
3) Tracking individual project phases with a plethora of mandatory finish dates and milestones.
The scope of application of the waterfall model:
(1) The user's needs are very clear and comprehensive, and there is no or little change in the development process; (2) The developer is familiar with the application field of the software;
(3) The user's use environment is very stable;
(4) The requirements for user participation in development work are very low.
The advantages of the rapid prototyping model:
(1) It can get a relatively good definition of requirements, and it is easy to adapt to changes in requirements;
(2) It is conducive to the synchronization of development and training;
(3) The development cost is low, the development cycle is short, and it is more user-friendly.
Disadvantages of rapid prototyping model:
(1) Customers and developers have different understandings of prototypes;
(2) Accurate prototyping is difficult;
(3) It is not conducive to the innovation of developers.
The scope of use of the rapid prototyping model:
(1) Those who are familiar with the field to be developed and have rapid prototyping tools;
(2) The prototype model can be used as a software development model during project bidding;
(3) Product migration or Prototype models are ideal when upgrading, or when customizing an existing product prototype.
Advantages of the incremental model:
(1) The advantage of using the incremental model is that the personnel allocation is flexible, and there is no need to invest a lot of human resources at the beginning;
(2) If the core product is very popular, the manpower can be increased to achieve the next increment;
(3) ) can release some functions to customers first, which acts as a sedative for customers.
Disadvantages of the incremental model:
(1) Parallel development components may encounter the risk of not being able to integrate, and the software must have an open architecture;
(2) The flexibility of the incremental model can greatly improve its ability to adapt to such changes. It is suitable for the waterfall model and the rapid prototyping model, but it is also easy to degenerate into a model that changes while doing, so that the control of the software process loses its integrity.
The scope of use of the incremental model:
(1) The incremental model is very suitable for upgrading existing products or developing new versions;
(2) For products with strict completion deadlines, the incremental model can be used;
(3) For all The field of development is more familiar and there is a prototype system, and the incremental model is also very suitable.
Advantages of the Spiral Model:
(1) Flexibility in design, changes can be made at various stages of the project;
(2) Large-scale systems are built in small segments, making costing simple and easy;
(3) Customers are always involved The development of each stage ensures that the project does not deviate from the correct direction and the controllability of the project;
(4) As the project progresses, the client always has the latest information of the project, so that he or she can effectively interact with the management.
Disadvantages of the spiral model:
(1) The use of the spiral model requires considerable experience and expertise in risk assessment. In the development of high-risk projects, if the risks cannot be identified in time, it will inevitably cause heavy losses; (2) Too many The number of iterations increases development costs and delays commit times.
Scope of use of the spiral model: The spiral model is only suitable for large-scale software projects.
15. Copyright
16. Patent rights
