The nature of processor interrupts, the difference between
hard interrupts, soft interrupts, and exceptions Hard interrupts, hardware outside the CPU, introduced interrupts, random.
Soft interrupt, the software running in the CPU executes the interrupt instruction, and the introduced interrupt is designed in advance.
Interrupt Masking
Hard interrupts are maskable, but soft interrupts cannot be masked.
Interrupt Nesting
Whether hard interrupts can be nested and whether they have priority (determined by the hardware design system).
Softirqs cannot be nested, but softirqs of the same type can be executed in parallel on different CPUs.
- Origin of Interrupt
In 1956, the ERA 1103A computer system introduced an interrupt mechanism.
ERA 1103A is used to receive and process wind tunnel test data, and then return the data processing results to the wind tunnel, and so on. However, the preparation time for wind tunnel data is relatively long, and the ERA 1103A can only be in a waiting state. This time is wasted in vain. In order to improve the utilization rate of ERA 1103A, it leads to an interruption line to run other programs during the period of waiting for wind tunnel data. When the wind tunnel data arrives, the interruption line tells ERA 1103A to stop the current work and receive the wind tunnel. data.
Above is the original interrupt design prototype.
ERA 1103A computer system
2. Interrupt classification
The concept of interrupts in modern processors has become more and more extensive and is not limited to external device interrupts.
The meaning of the interrupt is that while the CPU controls the external device, the external device can also efficiently "control the CPU". This design idea extends to three aspects: external hardware control CPU, software control CPU, and CPU operation management.
Therefore, it is more appropriate to use the events event representation, but in the usual description, the word interrupt is basically still used.
The categories of events are shown in the figure below, mainly including interrupts and exceptions. External hardware control CPU corresponds to hardware interupt, software control CPU corresponds to software interrupt, and CPU operation management corresponds to exception.
2.1 hardware interrupt
Hardware interrupt is the most frequently contacted type of event, such as mouse, keyboard, network card, etc. can generate hardware interrupt. Because the CPU does not know when the external hardware device generates the hardware interrupt request, and does not know the premise of generating the hardware interrupt in advance, therefore, the hardware interrupt is an asynchronous event.
The CPU and external IO devices transmit hardware interrupt signals through one or more hardware connections. This hardware wiring can be implemented inside the SoC or on an external PCB.
After the interrupt controller IP is integrated in the CPU, the interrupt signal lines of each IO device can be connected to the interrupt controller inside the SoC. For example, the very common ARM GIC can not only handle hardware interrupts of external IO devices, but also handle hardware interrupts between CPUs. Its internal structure is shown in the following figure:
The internal GIC
external IO device can be connected to the CPU through the interrupt control chip, which is usually called PIC.
The most representative of such interrupt control chips should be Intel 8259, which can be found in the microcomputer principle course.
Intel 8259 PIC
This is a Programmable Interrupt Controller (PIC) designed for the Intel 8085 and Intel 8086 microprocessors. The 8259 combines multiple interrupt input sources into a single interrupt output to the main microprocessor, extending the interrupt levels available in the system beyond one or two levels on the processor chip. This hierarchical, scalable interrupt architecture design concept is still visible in today's high-performance GICs.
2.2 software interrupt
Assuming that the operating system prevents unprivileged code from directly accessing system resources, how can applications access these protected resources? At this point, a software interrupt can accomplish this. Software interrupts occur when an application terminates or requests some service from the operating system. If a system call is included in the software code, software interrupt can be understood as a synchronous event.
When the CPU receives a software interrupt signal, it may temporarily switch control to an interrupt handler program, and the process in the kernel that was suspended by the interrupt (for example, a running instance of a program) will resume after the interrupt is accepted.
The application program completes the communication between the application layer and the operating system kernel based on the system call, and realizes the control of the CPU.
2.3 Exceptions
CPU exceptions occur in various error situations, such as when accessing invalid memory addresses or dividing by zero, in order to respond, an exception handling mechanism is generated. Processors of different architectures have different definitions of exception types, but the core idea is that the CPU work process encounters an unallowable error or a forced stop instruction, etc., and the exception can be classified as follows.
For Faults exceptions, it usually does not affect the continued operation of the software code. Such exceptions mainly include:
o Division by 0 operation
o Invalid opcode
o Device unavailable
For Traps exceptions, JTAG debug is more common. When the CPU receives the debug command, it will enter the exception mode. Such exceptions mainly include:
o breakpoint
o overflow
o debug instruction
For Abort exception, the more common one is instruction fetch exception. When the instruction to be executed is not correctly obtained from RAM, the CPU enters the Abort exception. Such exceptions mainly include:
o memory fetch errors
o bus errors
o cache errors
Reference link
https://mp.weixin.qq.com/s/hG2Zp8imtvTATjclsUYVEw
https://blog.csdn.net/weixin_44124323/article/details/115914946