（二）多路选择器

使用always（testbench不会变）

`timescale 1ns/10ps

module device(a,b,sel,y);
input a,b;
input [1:0]sel; //括号要写在前面
output y;
reg y;
always@(a or b or sel)//敏感变量列表要写全
begin
	if(sel==1)
		begin
			y<=a^b;
		end
	else
		begin
			y<=a&b;
		end
end
endmodule


module device_tb;
reg [3:0]absel;//输入使用reg
wire y;//输出使用wire
	device  device(.a(absel[0]),.b(absel[1]),.sel(absel[3:2]),.y(y));//a，b，sel都要是程序里面定义的

	initial begin
				absel<=0;
				#200 $stop;
		end
		always #10 absel<=absel+1; //不要加@
endmodule

使用assign

`timescale 1ns/10ps

module device(a,b,sel,y);
input a,b,sel;
output y;
assign y=sel?(a&b):(a^b);
endmodule


module device_tb;
reg a,b,sel;
wire y;//输出使用wire
device  device(.a(a),.b(b),.sel(sel));//a，b，sel都要是程序里面定义的
initial
	begin
		a<=0;b<=1;sel<=0;
		#10 a<=0;b<=0;sel<=0;
		#10 a<=0;b<=1;sel<=0;
		#10 a<=0;b<=0;sel<=0;
		#10 a<=1;b<=1;sel<=1;
		#10 a<=1;b<=1;sel<=0;
		#10 a<=1;b<=0;sel<=1;
		#10 $stop;	
	end

endmodule

case语句在多路选择中的应用

`timescale 1ns/10ps

module device(a,b,sel,y);
input a,b;
input [1:0]sel;
output y;
	reg y; //always 语句块里面赋值的变量需要是reg型
	always@(a or b or sel)//三个为敏感变量，组合逻辑输入
	begin 
		case(sel)
		2'b00:begin y<=a&b;end
		2'b01:begin y<=a|b;end
		2'b10:begin y<=a^b;end
		2'b11:begin y<=~(a^b);end
		endcase
	end 
endmodule


module device_tb;
reg a,b,sel;
wire y;//输出使用wire
device  device(.a(a),.b(b),.sel(sel));//a，b，sel都要是程序里面定义的
initial
	begin
			 a<=0;b<=1;sel<=2'b00;
		#10 a<=0;b<=0;sel<=2'b10;
		#10 a<=0;b<=1;sel<=2'b11;
		#10 a<=0;b<=0;sel<=2'b00;
		#10 $stop;
		
	end

endmodule