Zynq 7000 SoC is the industry's first All Programmable SoC
Composition:
PL (FPGA part)
PS (ARM part)
Efficient interface for PL and PS data transmission : AXI and ACP
PS: Processing System, the part of ARM's SOC that has nothing to do with FPGA.
PL: Programmable Logic (Progarmmable Logic), FPGA part.
APU: Application Processor Unit (Application Processor Unit). Located in the center of the PS.
SCU: Snoop Control Unit, used to maintain the consistency of the data Cache between the dual cores.
Main tool: Vivado (PL part implementation)
Common steps:
1. Create New Project, select the chip
2. Create Block Design
3. Add IP, and configure and connect according to the hardware schematic diagram
4. Right-click the .bd file, click Generate Output Products
5. Right-click the .bd file and select Create HDL Wrapper to generate the top-level file.
6. Click Run Synthesis
in the left navigation bar. Click Run Implementation
8 in the left navigation bar. Click Generate Bitstream
9 in the left navigation bar . File– Export–Export Hardware, pay attention to select Include bitstream※
10, File–Launch SDK
Main tools: SDK (part of PS implementation, code debugging and project download)
Common steps:
1. On the basis of the project established by Vivado, File-New-Application Project, create a FSBL project
2. File-New-Application Project, Create a project and write the code
3. Click Xilinx Tools-Create Zynq Boot Image, add three files [fsbl.elf, PL.bit, usercode.elf] in turn, and then click Create Image to generate a downloadable bin file.
4. Power on the board and connect to JTAG. Click Xilinx Tools-Program Flash, select the .bin file generated in the previous step, and then click Program to wait for the end of the programming.
The actual operation can be clicked: dual CPU test