UART / IIC / SPI / WIRE
1. The UART of Qiu Qianzhang's light work on water
Qiu Qianzhang in the Legend of the Condor Heroes said, UART is my light power to float across the river. If you want to cross the river (communication), place the hidden piles in advance. When walking, the pace is fixed according to the pile distance (the baud rate is determined in advance). If the stride is too large or too small, it will fall into the water. In order not to be seen through by the second brother Qiu Qianren, the guards can be arranged to monitor the notification on the other side, and the performance will start (flow control) without risk. In order to ensure that the stepping point is accurate, a thick wooden stake with special markings is placed at a distance.
UART Universal Asynchronous Receiver/Transmitter, the communication parties are connected to three wires, RX, TX and GND, TX is used to send data, RX is used to receive data, the two sides send and receive cross docking, and support full duplex mode.
Because there is no clock control, when will the data be sent and the other party will receive it correctly?
For example, when A sends data to B, A.TX and B.RX. remain at 1 during normal idle time. When A.TX sends 0 as the start bit, tell B please note that I want to send data. Then it starts to send data. The data bits are configurable, usually 5 bits, 6 bits, 7 bits, and 8 bits. After one frame of data is sent, A.TX gives a high level to tell B.RX that I have finished sending a frame. If the check digit is turned on and a check digit is sent before the stop bit is sent, the check digit is generally not needed, and the probability of errors in short-distance wired transmission is very small. If there is still data, repeat the previous operation.
General software configuration serial port, there are baud rate, data bit, stop bit, parity bit, flow control. Respectively indicate the transmission speed, the length of a frame of data, and the notification to stop after sending, whether to verify after sending, and whether to send control. It seems that there are many parameters. According to personal experience, it is generally fixed 8 data bits, 1 stop bit, no parity, no flow control, just configure the baud rate.
UART does not have a clock to control the timing of data capture. It relies on the definition of the baud rate before communication. Both parties read and write data bits at a defined frequency. Just like the floating on the water, once the dark pile is installed and fixed, it must walk at a fixed step length, otherwise It will go wrong and fall into the water.
UART can be used in water floating projects, but the transmission efficiency is limited, generally as high as 921600. If it is higher, there may be errors. If you continue to increase it, you will fly at high altitude. In the end, Qiu Qianzhang hopes to walk freely at high altitude and wants to climb Huang Rong to ride. The big eagle escaped, fell accidentally, and died in a flying accident.
2. Tell you, do you dare to agree? I2C
As the boy who watched the silver stove, the king of silver corner knows I2C best. I will call you out of thousands of people. If you agree, you will be unlucky (the slave address is correct to communicate).
IIC (Inter Integrated Circuit) two wires, a clock line SCL and a data line SDA, so it is half-duplex communication, master-slave mode, support one-to-many, a silver horn king can deal with a group of monkeys, each monkey has a different name (The I2C address of the slave device is different), whoever is called will be taken away by Zijin Gourd.
Assuming that the master A sends data to the slave B (A.SCL connects to B.SCL, A.SDA connects to B.SDA), according to the application, A can connect to B, C, D at the same time. When idle, the levels on SDA and SCL are both high.
Start and stop Start condition S: When SCL is high, SDA switches from high to low; Stop condition P: When SCL is high, SDA switches from low to high. The start and stop conditions are generally generated by the host. The bus is in a busy state after the start condition. After a certain period of time in the stop condition, the bus is in an idle state again.
When idle, the levels on SDA and SCL are both high. A pulls SDA low first, and then pulls SCL low after SDA becomes low (the above two actions constitute the start bit of I2C), at this time SDA can send data, and at the same time, SCL sends a certain amount For periodic pulses, the relationship between SDA sending data and SCL sending pulses is: SDA must remain valid when SCL is high, and send the next bit when SCL is low (SCL will sample SDA on the rising edge) .
Transmission and response : 8-bit data is transmitted at a time. After 8-bit data transmission, A releases SDA, SCL sends another pulse (this is the ninth pulse), and triggers B to set SDA to low level to indicate confirmation (the low level is called ACK). Finally, SCL goes high first, and SDA goes high again (the above two actions are called end flags). If B does not set SDA to 0, then A stops sending the next frame of data.
The overall timing of each device on the I2C bus has a unique address. When a data packet is transmitted, the address bit is sent first, followed by the data. An address byte consists of 7 address bits (128 devices can be linked) and 1 indicator bit (7-bit addressing mode), 0 means writing, 1 means reading. Generally, the I2C addresses in the chip manual are all 7-bit addresses, and some are related to the level of a certain pin, and the host controls the last read and write bits.
Actual projects generally use the I2C library. Some libraries require 8-bit write addresses to be passed in, and some are 7-bit addresses. The interface function then distinguishes between read and write bits. Of course, the most stupid way is to periodically read a register address from 0 to 255. The address when the correct value is read is the correct slave address.
In general, I2C library is used. In addition to configuring the slave address, other timings such as start and end are not really concerned. You only need to configure the clock frequency. Generally, depending on the maximum support of the slave and the system clock of the host, it will be too high. Occasionally errors occur, and when there is no time requirement, the lower the clock, the more stable it is.
3. SPI of Murong Fudou's transfer to the stars
Murong Fu of Tianlong Babu: Although I am not as good as Qiao Feng who can use the Eighteen Palms of Jianglong, but he shot at me, I also used the other way to return to the other side, and the opponent will also be beaten back when outputting, hurting each other, he I have no choice but to stop the clock. Just like SPI, the master has turned on the clock to send data, and the slave is also outputting at the same time. When the clock stops, everyone will stop.
SPI Serial Peripheral Interface (Serial Peripheral Interface) master-slave mode, a high-speed, full-duplex synchronous communication bus. The standard SPI is 4 lines. SDI (data input), SDO (data output), SCLK (clock), CS (chip select, some are also called SS).
SDO/MOSI-master device data output, slave device data input, master output slave input; SDI/MISO-master device data input, slave device data output, master input slave output; SCLK-clock signal, generated by the master device; CS/ SS-slave device enable signal, controlled by the master device. When there are multiple slave devices, the master device selects one of the slave devices to communicate through the chip select pin. (I2C is realized by software protocol, and SPI is realized by hardware).
When the host controls the CS and opens the clock gate, both the host and the slave can start to put data bits or fetch data bits for interaction, but at what timing, there is a standard. According to the working requirements of the peripherals, the polarity and phase of the output serial synchronization clock can be configured. CPOL: Clock polarity selection, when SPI bus is idle, it is low level, when SPI bus is idle, it is high level CPHA: clock phase selection, when it is 0, sampling at the first transition edge of SCK, when it is 1. Sampling on the second edge of SCK
| mode | CPOL | CPHA |
|---|---|---|
| 0 | 0 | 0 |
| 1 | 0 | 1 |
| 2 | 1 | 0 |
| 3 | 1 | 1 |
There are four modes. Take mode 1 as an example, it is low when idle, the first clock jump sampling, that is, the rising edge reading sample, and the data is placed on the falling edge. If it is really unclear, there is still a stupid way. Try all the four modes at once to know the correct mode.
There is no limit on the number of digits of SPI transmission data, as long as you define the high-order or low-order before sending and receiving, high-speed transmission can be continued.
As before, if Qiao Feng stopped, Murongfu would not be able to use the effect of Jianglong’s Eighteen Palms, but he could scold Qiao Feng for being a Khitan dog in person. When Qiao Feng was angry, he would do his work, and Murongfu would succeed in trickery. . The translation of the three characters of Qidan dog into software term is to trigger an interrupt. The slave sends an interrupt to inform the host that I have something to come to me; the host can also perform regular query, but the usage is less.
4. Qiu Qianchi's jujube spitting skills and 1-wire
Qiu Qianzhang's third sister, Qiu Qianchi, was imprisoned underground. She sprayed the date pits on the jujube tree with her mouth, and the shaking of the tree would drop the jujube to satisfy her hunger. This date-core nail is a one-way operation. If you use too much force, the date core penetrates the jujube tree, the force is too light or the shot is missed, and the jujube tree does not respond, so it will be a tragedy if the date core is used up. It can be seen that this stunt looks simple, but in fact, there is precise control hidden behind it. The timing and position control must be perfect, such as 1-wire communication, single-wire control, and precise clock.
The 1-wire bus interface is simple, just one wire, generally internal open-drain output, external hardware pull-up.
1-wire uses a line to transmit four kinds of signaling components, including reset pulse and online response pulse reset sequence, write 0 time slot, write 1 time slot, read time slot. Except for the online response pulse, all other signals are sent by the bus master, and all the data and commands sent are the low order of the byte first. The data communication between the master and the slave is completed through time slots, and only one bit of data can be transmitted in each time slot. The data can be transmitted from the host to the slave through the write time slot, and the data can be transmitted from the slave device to the master through the read time slot. The time to complete a bit of transmission is called a time slot.
Refer to the peripheral chip manual for the general operation process, which is mainly the delay processing of different platforms. Software is required to implement the 1us delay interface, otherwise the data communication is abnormal.
5. Cheats and exercises
Each of the four interfaces has a suitable application scenario, and the occupancy of hardware ports, control requirements for software, and communication efficiency are also different. In particular, the first three are commonly used protocols and generally support hardware interfaces. Manufacturers also generally provide hal libraries, which gradually reduce the requirements for software developers. This also causes the code application to be very slippery, and the actual underlying principles are slightly lacking. Once the communication is abnormal or there are special requirements, it is impossible to start. For example, use GPIO to simulate UART, and use SPI to realize AT function.
Martial arts people generally pursue lost martial arts secrets. Just like software developers, when there is a problem, they always hope to summarize the experience of others, or the manufacturer’s technical support or source code, rather than creating new techniques. Swordsman Yue Buqun was originally the head of the Huashan School. He was proficient in Zixia magical arts and martial arts was top-notch. However, he did not continue to study his own internal skills. In order to ward off evil spirits, do software developers want to repeat the same mistakes?
Regardless of Jianzong and Qizong, first run the function and then reverse the code principle and implementation process, or first clarify the timing and principle and then code to realize the function. In the short term, Jianzong has high efficiency and fast processing capital; Qizong may be eliminated , Especially in snobbery small companies, do not pay attention to the cultivation of newcomers. If you combine the two into one, you can use it when the project is urgent. When you are free, you can specialize in research and summary, and learn from each other's strengths. This is the quality of a perfect developer.
There is no secret method for software development, and it depends on personal study and summary.