1. The necessity of non-contiguous memory allocation
1. Disadvantages of continuous memory allocation
(1) The physical memory allocated to a program is continuous
(2) The memory utilization rate is low
(3) There are external fragmentation and internal fragmentation problems
2. Advantages of non-continuous allocation
(1) The physical address space of a program is non-contiguous
(2) Better memory utilization and management
(3) Allow sharing of code and data (shared libraries, etc.)
(4) Support for dynamic loading and dynamic linking
* The main problem of non-continuous allocation is the management overhead itself
Second, the management method of non-contiguous physical memory
Physical memory management needs to consider such a problem: how to establish the conversion between virtual addresses and physical addresses. There are two solutions to this problem-software (expensive) and hardware. Therefore, it is necessary to focus on how to use the existing hardware to assist the management of non-contiguous physical memory. Segmentation and paging are the main hardware solutions.
1. Segmentation
There are different stack segments in the logical address. If these stack segments can be better distinguished and isolated, it will help us to better manage.
The purpose of segmentation: better separation and sharing.
Focus on two issues:
1.1 The segmented address space of the program
When 1234 is mapped from a logical address to a physical address space, the size and location become different.
Segmented logical view:
1.2 Segmented addressing scheme
Segment access mechanism: the program needs a two-dimensional two-tuple (s, addr) to access the memory address
[s_ segment number; addr_ offset within the segment]
Hardware implementation scheme: The CPU calls the logical address and finds the starting segment number and segment length of the physical address according to the segment table. After the MMU checks whether the segment number and segment length are legal, if it is illegal, it will display a memory abnormality, and if it is legal, it will address it correctly.
- The operating system establishes the segment table in advance
2. Paging
Most current CPUs use a paging mechanism.
In the segmentation mechanism, the segment size is variable, but the page size in the paging mechanism is fixed. The purpose is to facilitate the hardware to implement it accordingly.
2.1 Paging address space
Divide the physical memory into fixed-size frames (Frame, physical page): the size is a power of two
Divide the logical address space into pages of the same size (Page, logical page): the size is a power of two
(1) Frame
A memory physical address is a two-tuple (f, o)
[f_frame number (F bits, F refers to the number of bits remaining in the address space minus the number of bits occupied by o. There are 2 F frames in total ); o_ Intra-frame offset (S bits, S refers to the number of bits occupied by o, that is, the size of the page frame. Each frame has 2 S bytes)]
| Physical address = 2 S * f + o |
|---|
(2) Page
A logical address is a two-tuple (p, o)
[p_page number (P bit, 2 P pages); o_ page offset (S bit, each page has 2 S bytes)]
| Virtual address = 2 S * p + o |
|---|
2.2 Page addressing scheme: Convert logical address to physical address (pages to frames)
tool:
- Page table
- MMU/TLB
Page addressing mechanism: The CPU calls the logical address and finds the frame number of the physical address according to the page table.
- Different from the segmentation mechanism, the offset size within the page of the paging mechanism is fixed, so that it can be implemented on hardware in a more concise way, without considering the problem of different segment sizes in the segmentation mechanism.
- The page size of the logical address space is inconsistent with the frame size of the physical address space. Generally, the former is larger than the latter. The virtual address solves the problem of space size mismatch.
- Contiguous pages in the logical address space may become discontinuous when mapped to the physical address space, which helps reduce fragmentation.
- The operating system establishes the page table in advance
2.3 Page Table
2.3.1 Overview of page tables
Page table: the frame number stored with the page number as the index. (Flags | Frame num)
- The offsets of the physical address and the logical address are equal, and the frame numbers are not necessarily equal.
- The page table holds the mapping relationship between logical address and physical address.
- A series of attributes are stored in the page table, and there are attributes (0/1) to determine whether the physical space exists.
Performance problems of the paging mechanism
(1) Accessing a memory unit requires 2 memory accesses
- Once used to get page table entries
- Once to access data
(2) The page table may be very large
For example: if a 64-bit machine has 1024 bytes per page, what is the size of a page table?
- 2 54
--> A large logical address space may lead to a large page table
solution
- Caching: The most commonly used memory is stored closer to the CPU (such as TLB)
- Indirect (Indirection) access: split large space into small spaces (such as multi-level page tables)
2.3.2 MMU/TLB（translation look-aside buffer)（快表）
Structure: Key | Value
caches the recently accessed page frame conversion table entries.
- TLB is implemented using associative memory (associative memory)
- If the TLB hits, the physical page number can be obtained quickly
- If the TLB is missed, the corresponding entry is updated to the TLB
It is possible to avoid one access to the page table, so that the addressing overhead is reduced.
2.3.3 Two-level/multi-level page table
(1) The secondary page table
divides the page table into primary page table p1 (stores the page table, that is, the starting address of the secondary page table), secondary page table p2 (stores the [Flags | Frame num corresponding to each page table] ]).
Addressing in the manner of a secondary page table obviously requires one more page table access, which increases the overhead. But in this way of addressing, some page table entries that are not necessary to access do not occupy memory.
(2) Multi-level page table The
multi-level indirect page table is realized by dividing the page number into k parts, that is, the establishment of a page table "tree".
In general, multi-level page tables are an idea that saves space at the expense of time; TLB is an idea that saves time at the expense of space. The two complement each other and complement each other.
2.3.4 Inverted page table (inverted page table)
Idea: The size of the page table is not limited to the size of the logical address space, that is, there is no direct correspondence between the page table and the logical address space, but a certain relationship is established with the physical address space, that is, the frame number is used.
Page Registers structure based on Page Registers: [Frame number f | Page number P]
(1) Advantages
- The conversion table size is small relative to physical memory
- The size of the conversion table has nothing to do with the size of the logical address space
(2) Disadvantages
- The required information is reversed, that is, the page number can be found according to the frame number
- How to convert back? Find the frame number according to the page number
- Search for the required page number in the required reverse page table
The scheme based on associative memory is
similar to TLB. The page frame number corresponding to the page number can be searched in parallel.
Summary of the two schemes: The reverse page table design can be done very well, but the cost and cost are high, which makes it impossible to make it particularly large, and large storage will slow down the search speed. These problems make the reverse page table not practical enough.
Steps to search for the frame number corresponding to a page in the reverse page table
- If the number of frames is small, the page register can be placed in the associated memory
- Find the logical page number in the associative memory
- Success: The frame number is extracted
- Failure: page fault (page fault)
- Limiting factor:
- A large amount of associative memory is very expensive: difficult to complete in a single clock cycle; power consumption
Optimization scheme: scheme based on hash (hash) search
- With hash table: input page num, output frame num
- Need hardware help to support high-speed hash table calculation
- Need to build efficient functions
- In order to improve efficiency and resolve conflicts, it is necessary to add a running parameter PID (current running ID) to the hash table, so that a relatively concise hash function can be designed well and the corresponding frame number can be calculated.
(1) Advantages
- Not limited by the size of the logical address space, the capacity can be made small
- Not affected by the number of processes, only one page table is needed
(2) Disadvantages
- Hash collision occurs, that is, for one input, there are multiple outputs, and further analysis is needed at this time. The ID of the program can alleviate this conflict.
- When performing hash calculation, it is also necessary to fetch numbers from the reverse list in memory, and the overhead is still relatively large, so a mechanism similar to TLB is still needed for caching.