Simple understanding of Makefile 1
There are many articles about Makefile learning on the Internet, and each article has its own characteristics. Just for me, I still feel that some issues are not clear. Now I want to analyze from a zero-based perspective and learn Makefile with everyone.
All in all, it is to simplify complex issues!
[Function introduction] MakeFile can be regarded as a simple programming language, the essential purpose of its birth is to realize automatic compilation.
Taking the gcc-c compiler under Linux as an example, compiling a C language program requires the following steps:
1. Pre-processing to generate pre-compiled files (.i files):
gcc -E hello.c -o hello.i
2. Compiling to generate assembly code (.s files):
gcc -S hello.i -o hello.s
3. Assembling (Assembling), generate object file (.o file):
gcc -c hello.s -o hello.o
4. Link (Link), generate executable file:
gcc hello. o –o hello
If you want to complete the whole process in one step:
gcc hello.c -o hello
[Compile and link]
To get the final executable program, first compile the source file into an intermediate code file, which is .obj file under Windows, and .o file under UNIX\Linux, namely Object File, compile (compile) . Then combine a large number of Object Files into executable files and link them.
When compiling, what the compiler needs is correct syntax and correct declaration of functions and variables. For the latter, you usually need to tell the compiler where the header files are. As long as all the syntax is correct, the compiler can compile intermediate object files. Generally speaking, each source file should correspond to an intermediate target file (O file or OBJ file).
[Working method] Makefile
.C file -> .o file -> executable file
If you want to specify a specific Makefile, you can use the "-f" and "-file" parameters of make, such as: make -f Makefile or make --file Makefile
[Example introduction] MakeFile of Hello program
TOPDIR = ../
include $(TOPDIR)Rules.mak
EXTRA_LIBS +=
EXEC = $(INSTALL_DIR)/hello
OBJS = hello.o
all: $(EXEC)
$(EXEC): $(OBJS)
$(CC) $(LDFLAGS) -o $@ $(OBJS) $(EXTRA_LIBS)
install:
$(EXP_INSTALL) $(EXEC) $(INSTALL_DIR)
clean:
-rm -f $(EXEC) *.elf *.gdb *.o
[Explanation]
CC specifies the macro of the compiler
EXEC represents the macro of the generated executable file name
OBJS object file list macro
LDFLAGS connection parameter macro
All: Compile the main entrance
Clean: Clear the compilation results
Install: Install the successfully compiled executable file into the system directory, generally the /usr/local/bin directory
[Makefile rules]
There are mainly five things in the Makefile:
explicit rules,
implicit rules,
variable definitions,
file instructions,
comments
1. Explicit rules.
Explicit rules explain how to generate one or more object files. This is clearly pointed out by the writer of the Makefile, the files to be generated, the dependent files of the files, and the generated commands.
Such as: foo.o: foo.c defs.h dependency relationship
gcc -o foo.o foo.c The method (method) of generating the target
2. Implicit rules.
Since our make has the function of automatic derivation, the obscure rules allow us to write Makefile more crudely and concisely, which is supported by make.
Such as: foo.o: foo.c (The .o file itself derives the dependent file with the same name.c.)
3. The definition of variables.
In the Makefile, we need to define a series of variables. Variables are generally strings. This is a bit like a macro in the C language. When the Makefile is executed, the variables in it will be expanded to the corresponding reference positions.
Such as: H: =foo.c gcc -o foo.o $(H) (Assignment can use: = or directly =)
4. File instructions.
It includes three parts, one is to reference another Makefile in a Makefile, just like the include in C language; the other is to specify the effective part of the Makefile according to certain circumstances, just like precompilation in C language #if is the same; another is to define a multi-line command.
5. Notes.
There are only line comments in the Makefile, which is the same as the shell script of UNIX. The comment uses the "#" character, which is like the "//" in C/C++ and Java.
The commands in the Makefile must start with the [Tab] key.