uvm_primer notes ch2

ch2 first build a testbench according to the traditional mode

overview

Contains a simple dut, a top file,
dut is a two-input calculator, input AB, then there is an operator input op, start indicates the start of the calculation (different operations require different time), and the done signal indicates the operation At the end, at the same time, the result of AB running OP is given in result.
This blog does not support verilog code,
so use java format code instead, because the following uvm is very similar to java

   typedef enum bit[2:0] {
    
    no_op  = 3'b000,
                          add_op = 3'b001, 
                          and_op = 3'b010,
                          xor_op = 3'b011,
                          mul_op = 3'b100,
                          rst_op = 3'b111} operation_t

Use enumerated data to define the type operation_t of op;

Covergroup is used in the code, this part can be ignored first;

In the code, the three functions of incentive generation, code coverage check, and scoreboard are all written into one file;

Two functions that generate data and op

Two functions are used, and the function does not consume simulation time ;

Data and operators used to generate incentives

   function operation_t get_op();
      bit [2:0] op_choice;
      op_choice = $random;
      case (op_choice)
        3'b000 : return no_op;
        3'b001 : return add_op;
        3'b010 : return and_op;
        3'b011 : return xor_op;
        3'b100 : return mul_op;
        3'b101 : return no_op;
        3'b110 : return rst_op;
        3'b111 : return rst_op;
      endcase // case (op_choice)
   endfunction : get_op

   function byte get_data();
      bit [1:0] zero_ones;
      zero_ones = $random;
      if (zero_ones == 2'b00)
        return 8'h00;
      else if (zero_ones == 2'b11)
        return 8'hFF;
      else
        return $random;
   endfunction : get_data

delay

   initial begin : tester
      reset_n = 1'b0;
      @(negedge clk);
      @(negedge clk);
      reset_n = 1'b1;
      start = 1'b0;

@ (negedge clk); a is delayed until the falling edge of the clock , and provides a delay similar functions # 5

Disadvantage

1. Putting all the functions into one file will not be good for future maintenance and reuse of the code;
2. Code design advocates making a single function into one file, such as separating incentives/scoreboard/coverage checks into different files