1. Introduction to Interrupt Binding
1. Introduction to interrupts
In a computer, an interrupt is an electrical signal that is generated by hardware and sent directly to the interrupt controller, and then the interrupt controller sends an interrupt signal to the CPU. After the CPU detects the signal, it interrupts the current work and processes the interrupt signal. The CPU will notify the operating system that an interrupt has been generated, and the operating system will handle the interrupt. There are two common interrupt controllers: programmable interrupt controller 8259A and advanced programmable interrupt controller (APIC). 8259A is only suitable for a single CPU. Under the multi-CPU and multi-core SMP system, in order to make full use of the SMP architecture and pass interrupts to each CPU on the system to better achieve parallelism and improve performance, Intel has introduced advanced programmable interrupt control器(APIC).
Interrupt is a way that hardware initiates communication with the CPU. Polling is the CPU periodically inquires about the hardware status and then performs corresponding processing.
Every hardware device (such as hard disk, network card, etc.) needs to communicate with the CPU so that the CPU can process hardware requests. The phenomenon that the hardware device actively disturbs the CPU is called a hardware interrupt.
In the operating system, each hardware device is assigned an IRQ number, and the interrupts of different hardware can be distinguished by a unique IRQ number.
2. Introduction to interrupt binding
Interrupt binding is to set the CPU Affinity of the interrupt so that the interrupt is only responded to on the specified CPU core.
Hardware interrupts occur frequently and consume CPU resources very much. Under multi-core CPU conditions, if a large number of hardware interrupts are allocated to different CPU core processing, performance can be well balanced. Usually there are multiple CPU cores, multiple network cards, and multiple hard disks on the server. If network card interrupts can monopolize 1 CPU core and disk IO interrupts monopolize 1 CPU core, it will greatly reduce the single CPU load and improve overall processing efficiency. .
By default, Linux interrupt response will be evenly distributed to all CPU cores, and new data and instruction caches will inevitably occur, and conflicts with the original processes on the CPU core will occur, causing interrupt response delays and affecting process processing time. In order to solve this problem, the interrupt (or process) can be bound to the specified CPU core, and the instruction code and data required by the interrupt (or process) have a greater probability of being located in the specified CPU local data and instruction cache, without the need for new Write cache, thereby improving the processing speed of interrupt response (or process). Bind a process and its related interrupts to the same CPU core to share the cache and improve program performance; bind interrupts and processes that are not related to each other to different CPU cores to avoid conflicts and improve program performance .
Linux Kernel 2.4 began to support the allocation of different hardware interrupt requests (IRQ) to specific CPUs. The binding technology is called SMP IRQ Affinity.
3. Interrupt the bound application
For file servers and web servers, binding different network card IRQ balances to different CPUs will reduce the load of a CP and improve the overall interrupt processing ability of multiple CPUs; for database servers, tie the disk controller to one CPU , Binding the network card to another CPU will improve the response time of the database and optimize performance.
A reasonable balance of IRQ interrupts according to the characteristics of your own production environment and applications will help improve the overall throughput and performance of the system.
Two, interrupt the binding process
1. Turn off the interrupt balance daemon
The interrupt balance daemon (irqbalance daemon) periodically distributes interrupts equally and fairly to each CPU core, which is enabled by default. In order to achieve interrupt binding, the interrupt balancing daemon needs to be shut down first. systemctl status irqbalance
Check the running status of the daemon. systemctl stop irqbalance
Turn off the interrupt balance daemon. The interrupt response will be handled by the CPU0 core by default. systemctl disable irqbalance
Canceling the interrupt balance daemon is
too tough to restart and shut down the interrupt balance daemon. It is possible to remove certain CPU cores from the interrupt balance daemon without closing the interrupt balance daemon.
2. Break off the balance daemon
You can modify the /etc/sysconfig/irqbalance configuration file to remove the specified CPU core from the list of interrupt balancing daemons, that is, the interrupt balancing daemon will no longer allocate interrupts to the corresponding CPU cores.
Set IRQBALANCE_BANNED_CPUS to prohibit the CPU hexadecimal mask managed by the interrupt balancing daemon. For example, if the CPU cores numbered 8-15 are separated from the interrupt balancing daemon, set as follows: The IRQBALANCE_BANNED_CPUS=0000ff00
CPU mask can have up to 64 bits, if the number of computer cores is If there are more than 32, you can use two 32-bit masks, separated by commas.IRQBALANCE_BANNED_CPUS=00000001,0000ff00
3. Bind the specified interrupt to the CPU
When interrupt binding, you need to close the system interrupt balance daemon. The systemctl stop irqbalance
current various interrupt response conditions of the computer are in the /proc/interrupts file. 
The first column is the interrupt ID number, the CPU N column is the response times of the interrupt on the nth CPU core, the penultimate column is the interrupt type, and the last column is the description.
Use the echo command to write the CPU mask into the /proc/irq/interrupt ID/smp_affinity file to modify the CPU affinity of an interrupt. For example, echo 0x0004 > /proc/irq /50/smp_affinity
bind the interrupt response of the network card to the CPU3 core.