What is the LIN bus? What is the difference between high-speed CAN, fault-tolerant CAN, and LIN bus?

Take a moment to read some of the basics of the LIN bus, extract the key points, and share with you here. Here you may want to ask "Aren't there all CAN buses? Where did this LIN bus come from?" In fact, the reason is very simple, that is, CAN bus is too expensive! If CAN bus is used everywhere, the bus of the whole vehicle The cost of the architecture will become very high! In some places such as car body electronic accessories (such as car windows, rearview mirrors, headlights, car locks, etc.), we do not need messages to be "high-speed" like those transmitted on the CAN bus! Major manufacturers have studied this LIN bus at a glance!

This article focuses on: Why is there LIN with CAN, the difference between CAN and LIN, where are the advantages of LIN?

1. What is LIN bus?

LIN (Local Interconnect Network) bus is a low-cost serial communication protocol based on UART/SCI (Universal Asynchronous Receiver/Serial Interface). Its goal is to locate the low-end communication between the vehicle body network module nodes, which is mainly used for the serial communication of smart sensors and actuators, which is exactly the part not required by the bandwidth and functions of the CAN bus.

2. CAN/LIN bus difference

Because the LIN network generally does not exist independently in the car, it is usually connected with the upper CAN network to form a CAN-LIN gateway node.

2.1. The master-slave relationship of LIN bus

The LIN bus adopts a single-wire transmission form, using the concept of single master and multiple slaves (is there support for active reporting?), the bus level is generally 12V, and the maximum transmission rate is limited to 20kbps. Due to the limitations of the physical layer, a LIN network can connect up to 16 nodes.

The bus task is responsible for:

  1. Schedule the transmission order of frames on the bus

  2. Monitor data and handle errors

  3. As a standard clock reference (not asynchronous communication?)

  4. Receive bus wake-up commands issued by slave nodes

The slave task cannot directly send data to the bus. After receiving the frame header sent by the master node, it is judged according to the information contained in the frame header:

  1. Send reply

  2. Receive reply

  3. Neither receive nor answer

Features of LIN

  1. The network consists of a master node and several slave nodes

  2. Using LIN bus can greatly reduce costs (CAN and Lin require transceivers, but Lin is a single-wire harness that saves)

  3. The transmission is deterministic, and the propagation time can be calculated in advance

  4. LIN has predictable EMC (Electromagnetic Compatibility) performance. In order to limit the strength of EMC, the LIN protocol specifies a maximum transmission rate of 20kbps

  5. The LIN bus provides signal configuration, processing, identification and diagnosis functions (these are not available in UART, but how does LIN implement it?)

3. LIN message frame structure

The LIN message frame includes two parts: a header and a response. The host is responsible for sending to the frame header; the slave is responsible for receiving the frame header and making analysis, and then decides whether to send a response, receive a response or not reply.

The (host) frame header structure includes a synchronization interval section, a synchronization section, and a PID section (protected ID) section. The response part includes a data section and a validation and section. Among them, the value "0" is the dominant level and "1" is the recessive level, which is similar to the CAN bus to play with embedded micropoint8. Implement "wire-and" on the bus: when the bus has at least one node sending a dominant level, the bus presents a dominant level; when all nodes send recessive levels or do not send information, the bus presents a recessive level. That is, the dominant level plays a leading role.

3.1.1. Synchronization interval

The synchronization interval segment is at least composed of 13-bit dominant levels, because all gaps in the frame or when the bus is idle, the bus maintains a recessive level state. So the synchronization interval can mark the beginning of a frame. The interval symbol of the synchronization interval segment is at least 1 recessive level.

3.1.2. Synchronization segment

LIN synchronization takes the falling edge as the judgment sign, and uses byte 0x55 (01010101b) for synchronization. A high-precision clock may not be used on the slave node, and the resulting deviation needs to be adjusted through the synchronization section.

3.1.3. PID segment

The first 6 bits of the protected ID are called the frame ID, and the two parity codes are called the protected ID. The frame ID has a value range of 0x00~0x3f, a total of 64, and the frame ID identifies the category and destination of the frame. The slave task will respond according to the frame header ID (receive/send/ignore response). The P0 and P1 are as follows:

The LIN bus divides the message into a signal carrying frame, a diagnosis frame, and a reserved frame according to the frame ID number.

PS: The slave response frame is a complete frame, which is different from the "response" in the (master node) frame structure!

3.1.4. Data segment

The data segment can contain 1-8 bytes, which contains two data types, signal (singal) and diagnostic messages (diagnostic messages). The signal is transmitted by the signal-carrying frame, and the diagnostic message is transmitted by the diagnostic frame.

The protocol does not specify which part of the data length code information is displayed (this is different from the CAN bus), and the content and length of the data are agreed in advance by the system designer according to the frame ID.

The data on the bus is sent out in the form of broadcast, which can be received by any node, but it is not useful for every node (the same as CAN). Specific to which node is responsible for publishing and receiving depends on the software configuration of the application layer. Generally, there is only one publishing node on the bus for a response in a frame, otherwise an error will occur. The event trigger frame is an exception, 0,1, and multiple publishing nodes may appear.

3.1.5. Validity and segment

Validation and segmentation are for validating the content of frame transmission. Validity test is divided into standard test and enhanced test. Whether the standard type or the enhanced type is adopted is managed by the host node, and the publishing node and the listening node determine which verification sum to use according to the frame ID.

4. LIN bus waveform

5. LIN bus communication

The above figure shows the communication mode of the LIN bus. It can be seen that the frame header is always released by the host node whenever the host node wants to release data, the entire frame is sent by the host node. When the slave node wants to publish data, the frame header part is published by the master node, and the response part is published by the slave node (how does the master know that the slave node wants to publish data, it must be that the master node has no data to send, so only the frame is sent Header?), so that other nodes can receive a complete message frame. It can be directly observed that LIN bus communication is initiated by the host node to play with embedded micropoint8. As long as the configuration of each node is reasonably specified, there will be no bus conflict (when an event triggers a frame conflict) Adopt the conflict resolution schedule).

Frame type

5.1. Unconditional frame

An unconditional frame is a frame that has a single publishing node. No matter whether the signal changes, the frame header will be unconditionally acknowledged.

As shown in the figure above, the publishing node in the response part of the frame ID=0x30 is the slave node 1, and the listening node is the master node, which is used when the slave node reports its own status to the master node; in the frame ID=0x31, the response part is the master node and the listening part As a slave node, the application is used in the master node to send a message to the slave node; the sending node in the response part of the frame ID=0x32 is the slave node 2, the listening node is the slave node 1, and the communication between the application and the slave node.

5.2. Event trigger frame

The event-triggered frame is a frame used when the master node queries whether the signal of each slave node changes in a frame gap. When there are multiple publishing nodes, the conflict is resolved through the conflict resolution schedule.

When the frequency of the slave node signal change is low, the master task will take up a certain amount of bandwidth to query the information of each node again and again. In order to reduce the bandwidth occupation, the concept of event-triggered frames is introduced. The main principle is: when the information status of the slave node does not change, the slave node can not respond to the frame header sent by the host; when multiple node information changes at the same time, the response event triggers the frame header at the same time to cause the bus Conflict. When the master node detects a conflict, it will query the conflict resolution schedule to send unconditional frames to each node in turn (unconditional frames can only be answered by one node) to determine the information status of the slave node.

Multiple unconditional frames associated with event-triggered frames need to meet the following 5 conditions:

The number of data bytes contained in the data segment is of the same length. Use the same validation and type. The first byte of the data segment is the protected ID of the unconditional frame, so that you can know which associated unconditional frame the response is sent from is different. The release of the slave node cannot be in the same schedule as the time trigger frame.

5.2.1. Sporadic frames

The sporadic frame is the frame that the host node starts sending to the bus when its own signal changes in the same frame time slot. When there are multiple associated response signal changes, arbitration is performed through the preset priority. Similar to event-triggered frames, occasional frames also define a group of unconditional frames. It is stipulated that occasional frames can only be issued by the host node.

There may be three situations in the transmission of sporadic frames:

  1. When the associated unconditional frame has no signal change, the host does not even need to send the frame header.

  2. When an associated unconditional frame signal changes, the frame is sent.

  3. When there are multiple unconditional frames with signal changes, they are sent sequentially according to the pre-specified priority.

5.2.2. Diagnostic frame

The diagnosis frame includes the master request frame and the slave response frame, which are mainly used for configuration, identification and diagnosis. The host request frame ID=0x3c, the publishing node of the response part is the master node; the slave response frame ID=0x3d, the publishing node of the response part is the slave node. The data segment is defined as 8 bytes, and the standard verification sum is used.

5.2.3. Reserved frames

The ID of the reserved frame = 0x3e and 0x3f, for future expansion needs.

5.3. Schedule

The schedule table is a frame schedule, which specifies the transmission order and transmission time of frames on the bus. The schedule is located on the host node, and host tasks are scheduled according to the needs of the application. There can be multiple schedules. Under normal circumstances, when it is the turn of a schedule to execute, it starts from the entrance of the schedule, and when it reaches the last frame of the schedule, it returns to The first frame of the current schedule starts to execute the embedded micropoint8, and it may be interrupted when the execution reaches a certain schedule, jump to another schedule and then return. For example, the event trigger frame is a typical example.

6. Implementation of the state machine

6.1. Host state machine

6.2. Slave state machine

The slave task is responsible for issuing or receiving the response status of the frame, including connecting two state machines: the synchronization interval section and the synchronization section checker, and the frame processor.

6.3. Slave task state machine


1. Analyze the impact of "interpretability" on artificial intelligence from an embedded perspective!

2. [MCU] Register, standard library, HAL library, LL library, so many libraries! How do you ask me to choose?

3. How many steps are there to develop embedded projects with Linux?

4. How does the program itself know its size? This is a question of whether a chicken lays an egg or an egg lays a chicken!

5. Domestic integrated development environment helps domestic RISC-V break the monopoly of foreign giants in chip technology

6. When doing embedded development, how do you realize LCD display?

Disclaimer: This article is reproduced online, and the copyright belongs to the original author. If you are involved in the copyright issues of the work, please contact us, we will confirm the copyright based on the copyright certification materials you provide and pay the author's remuneration or delete the content.

Guess you like

Origin blog.csdn.net/DP29syM41zyGndVF/article/details/110297485