It turns out that SPI is not as simple as I thought

Previous words

The day before yesterday, a reader wrote in a private message that the article I shared misled him, and then unfollowed it, so that I wanted to reply to what he wrote incorrectly or what he wrote incorrectly, but I couldn’t reply, although I received a little Strikes, but will still insist on learning, summarizing and sharing. The obstacles are long and there will inevitably be mistakes and omissions;

Previous words
table of Contents
First talk about the serial port
SPI communication protocol
SPI features
Mode number
Multi-slave mode
Pros and cons
Programming realization

First talk about the serial port

I wrote an article about UART, Universal Serial Asynchronous Communication Protocol. If you are interested, please refer to " I Bet! You don’t know UART yet; because UART does not have a clock signal, it cannot control when to send data, nor can it guarantee that dual-transmitters receive data at exactly the same speed. Therefore, if both parties receive and send data at different speeds, problems will arise.

To solve this problem, UART adds extra start and stop bits to each byte to help the receiver synchronize when data arrives;

Both parties must also reach a consensus on the transmission speed in advance (set the same baud rate, for example, 9600 bits per second).

A small difference in the transmission rate is not a problem, because the receiver will resynchronize at the beginning of each byte. The corresponding agreement is shown in the figure below;

Serial port transmission process

If you notice that the above figure is 11001010not equal to 0x53, this is a detail. The serial protocol usually sends the least significant bit first, so the least bit is on the far left LSB. The lower nibble is actually 0011 = 0x3, the upper nibble is 0101 = 0x5.

Asynchronous serial works very well, but requires additional start and stop bits when each byte is sent, and there is a lot of overhead in the complex hardware required to send and receive data.

It is not difficult to find that if the speed set by the receiving end and the sending end are inconsistent, the received data will be garbage (garbled).

Now let's talk about the advantages of SPI protocol.

SPI communication protocol

So we wondered if there is a better way of serial communication; compared to UART, SPIthe way of working is slightly different.

SPIIt is a synchronous data bus, which means that it uses a separate data line and a separate clock signal to ensure perfect synchronization between the sender and the receiver .

The clock is an oscillating signal that tells the receiver to sample the signal on the data line at the exact timing.

The side that generates the clock is called the master , and the other side is called the slave . There is always only one master (in general, it can be a microcontroller/MCU ), but there can be multiple slaves (detailed later);

The timing of data collection may be the rising edge (from low to high) or the falling edge (from high to low) of the clock signal .

It depends on the configuration of SPI;

The overall transmission can be roughly divided into the following processes:

The host first NSSpulls the signal low to ensure that it starts to receive data;
When the receiving terminal upon detecting an edge of a clock signal, it will be immediately read data line signals, thus obtained a data (1 bit);

Since the clock is sent with the data, it is not important to specify the transmission speed of the data , although the device will have the highest speed it can run (we will discuss choosing the appropriate clock edge and speed later).
When the host sends to the slave : the host generates the corresponding clock signal, and then the data is sent from the signal line to the slave one by oneMOSI ;
The host receives data from the slave : if the slave needs to send data back to the host, the host will continue to generate a predetermined number of clock signals, and the slave will send the data through the MISOsignal line;

The details are shown in the figure below;

SPI timing

Note that SPI is "full duplex" (with separate sending and receiving lines), so data can be sent and received at the same time, and the receiving hardware of SPI can be a simple shift register. This is much simpler and cheaper than the complete UART required for asynchronous serial communication;

SPI features

The SPI bus includes 4 logic lines, which are defined as follows:

MISO : Master input slave output host input, slave output (data comes from the slave);
MOSI : Master output slave input Host output, slave input (data comes from the host);
SCLK : Serial Clock serial clock signal, generated by the master and sent to the slave;
SS : Slave Select Chip selection signal, sent by the master to control which slave to communicate with, usually a low-level active signal.

Other manufacturers may follow other naming rules, but in the end they refer to the same meaning. The following are some commonly used terms;

MISO may be SIMO, DOUT, DO, SDOor SO(host side);
MOSI may be SOMI, DIN, DI, SDIor SI(host side);
NSS can also be CE, CSor SSEL;
SCLK can also be SCK;

This article will be explained according to the following names[MISO, MOSI, SCK，NSS]

The figure below shows a typical SPI connection between a single master and a single slave.

Master-slave connection

Clock frequency

The host on the SPI bus must be configured at the beginning of communication and generate the corresponding clock signal. In each SPI clock cycle, full-duplex data transmission occurs .

Host MOSIsending a data line, reading it from the machine, while the slave MISOtransmits a data line, the host reads it.

Even if only one-way data transmission is performed, this order must be maintained. This means that whatever data is received, something must actually be sent! In this case, we call it virtual data;

In theory, the clock rate can be any rate you want as long as it is practically feasible. Of course, this rate is limited by how much system clock frequency each system can provide, and the maximum SPI transmission rate.

CKP/Clock Polarity

In addition to configuring the serial clock rate (frequency), the SPI master also needs to configure the clock polarity .

According to the naming rules of hardware manufacturers, the clock polarity is usually written as CKP or CPOL . The clock polarity and phase together determine the way of reading data, such as reading data on the rising edge of the signal or reading data on the falling edge of the signal;

CKP can be configured as 1 or 0. This means that you can set the default state (IDLE) of the clock to high or low as needed. Polarity reversal can be achieved by a simple logic inverter. You must refer to the data sheet of the device to set CKP and CKE correctly.

CKP = 0: Clock idle IDLEis low level 0;
CKP = 1: Clock idle IDLEis high 1;

CKE /Clock Phase (Edge)

In addition to configuring the serial clock rate and polarity, the SPI master device should also configure the clock phase (or edge). Depending on the hardware manufacturer, the clock phase is usually written as CKE or CPHA ;

As the name implies, clock phase/edge, that is, the specific phase or edge of the clock signal when collecting data;

CKE = 0: SCKSampling at the first transition edge of the clock signal ;
CKE = 1: SCKSampling at the second transition edge of the clock signal ;

Clock configuration summary

In summary, the following figure summarizes all clock configuration combinations and highlights the time when the actual data is sampled;

The black line is the time when the data is sampled;

The blue line is the SCK clock signal;

The details are shown in the figure below;

Mode number

The configuration of SPI clock polarity and phase is usually called SPI mode , all possible modes follow the following conventions; the details are shown in the following table;

SPI Mode	CPOL	CPHA
0 [00]	0	0
1 [01]	0	1
2 [10]	1	0
3 [11]	1	1

In addition to this, we should carefully check the mode table included in the microcontroller data sheet to make sure everything is normal.

Multi-slave mode

As mentioned earlier, the SPI bus must have a master and there can be multiple slaves, so there are two specific ways to connect to the SPI bus:

The first method: multiple NSS

Usually, each slave needs a separate SS line.
If you want to communicate with a specific slave, you can NSSpull down the corresponding signal line and keep NSSthe state of other signal lines high; if you pull two NSSsignal lines low at the same time , garbled codes may appear, because the slave They may all try to MISOtransmit data on the same line, which eventually leads to garbled data received.

The specific connection method is shown in the figure below;

Multiple NSS connections

The second method: daisy chain

In the digital communication world, the device signal (bus signal or interrupt signal) is transmitted serially from one device to the next device, and the method of continuously looping until the data reaches the target device is called a daisy chain .

The biggest disadvantage of the daisy chain is that because it is a serial transmission of signals, once a device in the data link fails, the lower priority devices below it cannot be served;
On the other hand, the farther the slave is from the master, the lower the priority of obtaining the service, so it is necessary to arrange the priority of the slave and set the bus detector. If a slave is timed out, the slave will be short-circuited To prevent the entire link from crashing due to damage to a single slave;

The specific connection is shown in the figure below;

Daisy chain connection

The bold red line is the flow of data;

So the final data flow diagram can be expressed as:

Data flow diagram

SCK is the clock signal, and 8clks represents 8 edge signals;

Where D is data and X is invalid data;

Therefore, it is not difficult to find that the daisy chain mode makes full use of the function of SPI and its shift register. The entire chain acts as a communication shift register, and each slave copies input data to the output in the next clock cycle.

Pros and cons

Advantages of SPI communication

There are many reasons that make SPI stand out as a serial communication interface;

Full duplex serial communication;
High-speed data transfer rate.
Simple software configuration;
Extremely flexible data transmission, not limited to 8 bits, it can be any size word;
Very simple hardware structure. The slave does not need a unique address (unlike I2C). The slave uses the master clock and does not require a precision clock oscillator/crystal oscillator (unlike UART). No transceiver is required (unlike CAN).

Disadvantages of SPI

There is no hardware slave response signal (the host may send it from nowhere without knowing it);
Usually only supports one main device;
Need more pins (different from I2C);
No hardware-level error checking protocol is defined;
Compared with RS-232 and CAN bus, it can only support a very short distance;

Programming realization

The following is the HAL library code automatically generated by STM32 cubemx, which is relatively simple, and some of them are intercepted, as follows;

static void MX_SPI1_Init(void)
{
    hspi1.Instance = SPI1;
    hspi1.Init.Mode = SPI_MODE_MASTER;    //主机模式
    hspi1.Init.Direction = SPI_DIRECTION_2LINES; //全双工
    hspi1.Init.DataSize = SPI_DATASIZE_8BIT;  //数据位为8位
    hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;  //CPOL=0
    hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;   //CPHA为数据线的第一个变化沿
    hspi1.Init.NSS = SPI_NSS_SOFT;     //软件控制NSS
    hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;//2分频，32M/2=16MHz
    hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;   //最高位先发送
    hspi1.Init.TIMode = SPI_TIMODE_DISABLE;   //TIMODE模式关闭
    hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;//CRC关闭
    hspi1.Init.CRCPolynomial = 10;     //默认值，无效
    if (HAL_SPI_Init(&hspi1) != HAL_OK)    //初始化
    {
        _Error_Handler(__FILE__, __LINE__);
    }
}
    
//发送数据
HAL_StatusTypeDef  
HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, 
                 uint8_t *pData, 
                 uint16_t Size, 
                 uint32_t Timeout);
//接收数据
HAL_StatusTypeDef  
HAL_SPI_Receive(SPI_HandleTypeDef *hspi, 
                uint8_t *pData, 
                uint16_t Size, 
                uint32_t Timeout);

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