Logical inference

Verilog is a comprehensive front-end, HDL allows design to be expressed in a process-independent way. However, in the HDL description of the design, some restrictions have been comprehensively added. Not all HDL structures can be synthesized. Synthesis hopes to write HDL code in a specific way. It can also be said that synthesis is template-driven. The templates and coding modes used for synthesis are called coding styles. In order to get better results, designers must have an in-depth understanding of the coding style, logical inference, and the corresponding logical structure generated by DC; the
incomplete sensitive list
is the activation signal that actually triggers the process in the sensitive list.
Storage element inference
Storage element: latches and flip-flops. The latch is a level-sensitive storage element, and the flip-flop is edge-sensitive. As long as the enable of the latch is valid, the latch is transparent. Once the enable of the latch is invalid, the output Q keeps the value of the input D unchanged. The flip-flop is triggered by the rising or falling edge of the clock. The latch is a simple device, so it occupies a small area compared to the flip-flop. Latches are usually troublesome, because the existence of latches in the design will make it difficult to scan the DFT. In the design, latches should be avoided as much as possible and latches are recommended when needed.
Latch inference Latches are inferred
when the conditional statement is not fully specified. For example, the if statement in the else part is an example of not fully specifying the condition. The above statement allows DC to infer a latch enabled by the signal "weekend", the solution, assume the else statement, or use the default statement outside the if.

Register Inference
In order to support different clock edge types and reset mechanisms, DC provides various templates for register inference. When an edge is specified in the sensitive signal list, a register can be inferred. This edge can be a positive edge or a negative edge. Use the following template to infer a simple positive edge-triggered D flip-flop:

In order to infer the register with reset, add the reset signal to the sensitive list and write the reset logic in the always block. The following is a D flip-flop with asynchronous reset example of:

Simply remove the reset signal from the sensitive signal list to get a synchronous reset. Since the process block is triggered by the clock edge, it is only reset on the clock edge.

Multiplexer inference
Usually if statements are used to infer latches and priority encoders. The case statement is used to infer the multiplexer.
1. Multiplexer using case statement
In order to avoid inferring the latch in the case, the default statement is indispensable. For example, for a state machine, the default clause covers all states and causes a jump to the "start" state.
Three-state inference
When high impedance (Z) is assigned to the output, the three-state logic is inferred. It is generally not recommended to use tri-state logic at will, because:
1. Tri-state logic reduces testability;
2. Three-state logic is difficult to optimize because it cannot be buffered, resulting in max_fanout violations and heavy load connections;
advantages: significant savings area;