Introduction and use of Verilog's $readmemb and $readmemh

The format of $readmemx:

These two system tasks are used to read data from the file to the memory. It can be executed and used at any time during the simulation, and there are six formats in use:

$readmemb("<数据文件名>",<存贮器名>) $readmemb ("<数据文件名>",<存贮器名>,<起始地址>） $readmemb ("<数据文件名>",<存贮器名>,<起始地址>,<结束地址>)

$readmemh("<数据文件名>",<存贮器名>) $readmemh ("<数据文件名>",<存贮器名>,<起始地址>） $readmemh ("<数据文件名>",<存贮器名>,<起始地址>,<结束地址>)

In these two system tasks, the content of the data file to be read can only contain: blank positions (spaces, line breaks, tabulations, comment lines, binary or hexadecimal numbers. The numbers cannot contain bit width descriptions and format Description for $ readmemb and $ readmemh system tasks, each number can be binary and hexadecimal character. In addition, the numbers must be separated by a blank space or a comment line.

For the above six system task formats, 5 points need to be added:
(1) If there is no address description in the system task statement statement and data file, the default storage starting address is the starting address in the memory definition statement . The data in the data file is continuously stored in the memory until the storage unit is full or the data in the data file is exhausted.
(2) If the storage start address is specified in the system task, but the storage end address is not specified, the data will be stored from the start address until the end address in the memory definition statement.
(3) If both the end address and the start address are specified in the system task statement statement, the data in the data file will be stored in the storage unit according to the start address until the end address, regardless of the memory Define the start address and end address of the statement.
(4) If the address information is specified in both the system task and the data file, the address in the data file must be within the range declared by the address parameter in the system task. Otherwise, an error is displayed and the operation of loading data into the memory is interrupted.
(5) If the number of data in the data file is different from the number of data implied by the start address and end address in the system task, an error message should also be prompted.

Simple code:

module data_read;

reg [31:0] mem [0:11];
integer i;

initial $readmemh("./data.txt",mem);

initial begin
  for(i=0; i<12; i=i+1)
    $display("%d: %h", i, mem[i]);
end

endmodule

data.txt

// Hexadecimal values for $readmemh demo
 // can include comments with double forward slash (standard Verilog comment)
 // second 32-bit value
 // third value
 // etc.

// can break up into related groups, insert comments, etc.

8e700002
ae700001
1232fffa
1210fff9  // last value

note:

If the width of mem is adjusted to [15:0], an error will be generated and no output

Warning: (vsim-PLI-3406) Too many digits (8) in data on line 2 of file "./data.txt". (Max is 4.) : data_read.v(6)

If the width of mem is adjusted to [63:0], the result becomes

# 0: 0000000002328020

# 1: 0000000002328022

# 2: 0000000002328024

This comparison shows that the system tasks are read in rows.