Overview
Field programmable gate array (FiELD Programmable Gate Array, FPGA) devices have the advantages of high density, low power consumption, high speed, high reliability, etc., and have been widely used in aerospace, communications, industrial control, etc. FPGA processors are divided into soft cores and hard cores, and soft core processors are highly flexible and configurable.
Because the FPGA device adopts the SRAM process, the configuration data in the FPGA will be lost in the case of power failure, so a non-volatile memory is required to complete the design of the embedded system in conjunction with the FPGA. EPCS (Erasable Programmable Configurable Serial) Flash belongs to the serial interface Flash. It has the characteristics of simple interface, small size and convenient configuration. It is usually used to store FPGA configuration files and NiosII software executable codes. After a reasonable configuration, the system can read these files from EPCSFlash to start the entire system after power on.
In order to make the system more flexible, and to give full play to the flexibility and efficiency of FPGA, FPGA software and hardware programs need convenient update and upgrade functions; and when the product is formed, the JTAG and NiosII IDE tools are used to jointly complete the alignment. EPCS Flash update programming is very inconvenient. For this reason, this article combines the tools provided by ALTEra, and proposes a method for remotely updating FPGA configuration files and NiosII program files online.
2 System hardware structure
The system hardware structure is shown as in Fig. 1. The system mainly has three main parts: host computer system, FPGA system and EPCS Flash. The upper computer system provides the part of human-computer interaction. The FPGA system includes NiosII processor, EPCS controller, network and serial interface and other external interfaces. EPCSFlash is mainly used to store FPGA configuration files and Nios program image files. The upper computer system completes the communication work through the FPGA integrated network and serial interface.
FPGA adopts the EP3C40F48417N chip of Altera's CycloneIII system. It has the characteristics of low power consumption, high integration and easy to use. EPCS Flash uses Altera's EPCS16SI16N chip, which supports a variety of configurable clock sources, up to 100 MHz external clock source, and 16 Mb of storage space, which is enough to meet the storage needs of general FPGA configuration files and Nios program files.
3 Update program processing flow
The process of updating FPGA configuration files and NiosII applications is shown in Figure 2.
This method combines the FPGA configuration file and NiosII program file generated by the NiosII IDE, and programs it into a binary BIN file that can be directly executed and contains the FPGA configuration file and NiosII program file. Then the file is transferred from the host computer system to the application program of NiosII through the X-modem protocol. After receiving the complete BIN file, the NiosII application program writes the BIN file into EPCS Flash. Finally, the Nios II application program stops the watchdog, and the program restarts, which completes the process of remote online update of the FPGA.
4 Merging program files
The start of Nios II will go through two processes:
①The configuration process of the FPGA device itself. If NiosII is used in the internal logic, the configured FPGA contains NiosII soft core CPU.
②The application process of NiosII itself. Once the FPGA is configured successfully, NiosII is reset by the reset circuit in the logic and executes the code from the reset address.
Nios II IDE converts FPGA configuration files (.SOF files) and application programs (.elf files) into flash format files. The converted flash format file is a kind of S-Record format data, including the following areas: <type>< length><address><data><checksum>. The meaning of each field is as follows: <type> indicates the type of record; <length> indicates the length of the data; <address> indicates the starting address of data writing, and the length of this field depends on the value of <type>; <data > Means stored data; <checknum> means check digit.
The configuration file and the application program may have multiple sections, and a "program record" is inserted before each section. A "program record" is composed of two 32-bit data, one is a 32-bit integer, and the other is a 32-bit address, which respectively represent the length of the program segment itself and the runtime address of the program segment. Its storage layout is shown in Figure 3.
In order to update the FPGA configuration file and Nios II application program together when updating the program, merge the FPGA configuration file and Nios II application program into one file, and convert the merged Flash format file into a direct execution without address decoding Binary BIN file. The specific processing flow is shown in Figure 4.
In the process of merging programs, the length and destination address in the flash file are removed from the information used to parse the program, and the program image is converted from character format to binary format. The merged BIN file contains FPGA configuration file and Nios II application program, and Nios II application program is right behind FPGA configuration file, its storage layout is shown as in Fig. 5.
5 Nios II Update Program Module Processing the update program module in
Nios II program is mainly responsible for receiving the merged executable BIN file from the upper computer and writing the BIN file into EPCSFlash. The processing flow is shown in Figure 6.
5.1 The transmission of program files The
update program module and the host computer system in the Nios II application program use the X-modem protocol to transmit program files. X-modem protocol is an asynchronous transmission protocol widely used in network port and serial communication.
If an error occurs during program transmission, the update program module can exit the update program state by setting a timeout.
5.2 Reading and writing
to EPCS Flash Because the serial configuration device of EPCS Flash defines a special read and write protocol, the Nios II program can only be read through the HAL API (ApplICation Program Inter face) provided by ALTEra. Write Flash. The APIs for opening and closing Flash devices are: alt flash open_dev() and alt_flash_close_dev().
The APIs for operating Flash read and write are: alt_read_flash() and alt_write_flash_bLOCk(). The API to clear Flash is alt_erase_falsh_block().
Conclusion
This article aims to improve the convenience of FPGA remote update program, and proposes a remote online update FPGA program method based on EPCS Flash, so that FPGA-based products can be more easily maintained and upgraded in the application.