Feedback and triggers
Oscillator
Observe the following circuit:
The relay input and output of this circuit are together. When the switch is closed, the circuit will be connected, and after the circuit is connected, the switch affected by the relay will be opened. In this way, the entire circuit is continuously switched between connected and disconnected . If the beating switch is a metal reed, this circuit can be made into a buzzer or electric bell.
A circuit with only one inverter in this circuit loop is called an oscillator. The inverter continuously changes the state of the circuit. This transition takes some time. The oscillator does not require human intervention and can work spontaneously.
The output of the oscillator can be represented by the following figure:
The output changes regularly between 0 and 1. The oscillator is also called a clock because it can be counted by oscillation. The oscillator also has its own period and frequency.
Trigger principle
Observe the following circuit, which has a pair of NOR gates:
The connection of this circuit is special. The output of the left NOR gate is the right input, and the output of the right gate is the left input. This connection is called feedback.
When the upper switch is closed, the output of the left door becomes 0 and the output of the right door becomes 1, and the light bulb will be lit. When the above switch is turned off, the output of the left door is still 0, the output of the right door is still 1, and the light bulb is still on. This circuit is different from the previous situation. The switch on the upper left will not affect the lighting of the bulb, whether it is open or closed.
When the lower switch is closed, the output of the right door immediately becomes 0, and the light bulb goes out. At this time, the lower switch is turned off, and the light bulb is still off, because the previous operation has made the output of the left door always 1.
In summary, this circuit has two stable states, which are always off and always on. The same switching state may produce different circuit states. This type of circuit is called a trigger. If the light bulb of this circuit is on, it means that the last switch is the upper switch, if it is off, it means that the last switch is the lower switch, that is, it can remember certain information.
RS trigger
RS (Reset-Set) trigger is a relatively simple trigger, it is also the connection of two NOR gates:
Q represents the state of the output, and another Q is its negation. S is used to set (equivalent to setting Q to 1), R is to reset (equivalent to setting Q to 0). When adjusting S and R to 1, Q will change. When S and R are both 0, the state of Q will not change. The law can be summarized as the following table:
The situation when S and R are both 1 is illegal, which will cause the two Q states to be non-complementary. The RS trigger can be further simplified to the following symbols:
The characteristic of RS flip-flop is that it can infer which input terminal (S or R) the final state is 1.
D-type latch
Now we have to construct a circuit that can remember the signal at a certain time.
This circuit has two inputs, one is called the data terminal, and the other is called the holding bit. The holding bit is usually set to 0. At this time, the data terminal does not affect the circuit. The value will be remembered by the circuit. The truth table of the circuit at this time is:
Based on the RS trigger, plus two AND gates, a circuit system can be constructed:
When the hold bit is 0, neither reset nor set will affect the circuit. When the hold bit is 1, this circuit is an RS flip-flop. But this circuit has a drawback, that is, the input is three instead of two, we can regard reset and set as a pair of opposite numbers, because the rest of the situation can be regarded as not a valid input, then we can use a number Indicates reset and set, that is the data terminal, the data terminal indicates the set signal, the inverted value indicates the reset signal, the corresponding circuit is as follows:
When the holding bit is 0, the circuit is not affected. When the hold bit is 1, Q equals the value on the data side. If the holding bit becomes 0 again, the state of the circuit does not change, which is equivalent to remembering the value entered at the data terminal when the holding bit was last set to 1. Until the hold bit is set to 1, it can be remembered again.
This circuit is called a level-triggered D-type flip-flop (or D-type latch). The so-called level-trigger means that the circuit has a save function only when the hold bit is 1. The holding bit can also be called the clock terminal. If the data terminal is abbreviated as D and the clock terminal is abbreviated as Clk, the function table is as follows:
Improve addition with latches
When calculating the addition of three binary numbers, you can use the latch to remember the sum of the two numbers, and then add again to get the result.
We can make an 8-bit latch:
The upper 8 input terminals are D, the output terminal is marked with bit Q, and Clk is the clock. When the clock signal is 1, the input of D terminal is sent to the Q output. When the clock signal is 0, the 8-bit value will remain unchanged Until the clock signal is set to 1.
The modified 8-bit adder is as follows:
The switch saved by the flag bit Save is the clock input of the latch. When closed, the addition calculation result is stored. In the first calculation, the switch of the 2-1 selector is open. At this time, the two data come from the switch. When the selector switch is closed, it means that one of the data comes from the latch.
The circuit and truth table of the selector are as follows:
The use of latches can accomplish multiple additions. We need to add a clear switch to the original trigger:
When the clear signal is input 1, no matter what other inputs are, the final Q becomes 0. The improved adder is as follows:
First press the clear switch to make the output of the latch become 0, use the switch to input a group of arrays, then close the addition switch to save and output the first number. Then enter the second number and continue the addition. Repeated operations can be performed many times in succession.
Edge trigger
Edge-triggered clock input is different from level-triggered. Level-triggered is when the clock input is 1, the data will start to affect the circuit. Edge-triggered is that only when the clock input changes from 0 to 1, the data-end input will affect the circuit.
The edge-triggered D-type flip-flop is connected by two levels of RS flip-flops:
The clock input here controls two RS flip-flops. It is worth noting that the inverse operation is performed when the first one is controlled, which means that the data is saved when the signal is 0. At the same time, the input of the second flip-flop is the output of the first. When the clock signal is 1, the data of the second flip-flop can be saved. In short, only the moment from 0 to 1 can the data input be saved.
The truth table of this circuit:
The up arrow represents a positive transition, which is equivalent to the clock terminal changing from 0 to 1. This circuit can also be represented by the following symbols:
Edge type D flip-flop with preset and clear
As shown below:
When the preset signal is 1, Q becomes 1; when the clear signal is 1, Q becomes 0, the preset signal and the clear signal cannot be 1 at the same time, the principle of the trigger is the same as the ordinary edge trigger .
The truth table is as follows:
The following symbols can be used to represent this circuit:
Frequency divider and counter
Connect the oscillator and the edge-triggered D-type flip-flop:
The changes of several output terminals are as follows:
When the value of the clock keeps jumping, the value at the output also changes. If the frequency of this oscillator is 20 Hz, then the output frequency of Q is 10 Hz, so this circuit is called a frequency divider.
The output of the frequency divider can be used as the clock input of another frequency divider to divide the frequency again. For example, three frequency dividers are connected together:
When adding 0 and 1 to the signal change law:
That is, according to the clock input, different Q can be output at different times. These Q and Clk form a four-bit binary number. It can be found that the first number is 0000, then 0001, 0010, etc. The more frequency dividers connected together, the more binary digits can be expressed.
8 frequency dividers are connected together to form an 8-bit counter:
The reason why it is called a traveling wave counter is because the output of each flip-flop is the clock input of the next flip-flop, and the change is transmitted in the flip-flop one level at a time. The advanced counter is a synchronous parallel counter, and all outputs in this counter are changed at the same time.
The timing diagram of such a counter can be represented with 8 outputs, or they can be represented as a whole:
When the clock signal sends a positive transition, the output binary digit is incremented. Here, the frequency of the oscillator can be reversed according to the change law of the output digital.