1. The uvm_top.print_topology () function
Use the uvm_top.print_topology () function to print the uvm topology in the end_of_elaboration_phase of the test_base class.
Among them uvm_verbosity shows uvm printing redundancy.
2.
The waveform file module_name.fsdb generated in the waveform file uvm work is not the same as the waveform file $ {TESTCASE} _ $ SEED.fsdb after the name and path are replaced by the script. The former is not dumped.
In the top layer:
initial
begin
$ fsdbAutoSwitchDumpfile (1000, “module_name.fsdb”, 20);
$ fsdbDumpvars (0, tb_top);
$ fsdbDumpflush;
end
scripts:
$ RUN + fsdbfile +… /… / wave / $ {TESTCASE} _ * $ SEED.fsdb + fsdb + autoflush
3. Pull out the duv internal signal and compare it with the input and output.
In the scoreboard, you can directly pull out the duv internal signal for comparison. Here, you must check the complete level of the signal, tb_top… CLK / VALID / READY / DATA.
At this time, the standard writing method in the scoreboard is to set up multiple empty queues to store data, and separate the data collection and comparison. It is forbidden to collect data before comparing within a while (1) begin end to prevent timing problems.
4. The problem of opening verdi association code
Open verdi directly, after loading the waveform, inport design often has associated problems after importing the filelist. You can use a script to automatically associate the code after opening verdi.
Name the compiled log file runverdi.csh, and execute chmod + x to turn it into an executable file.
Open the file,
#! / Bin / env csh (set the default interpreter)
bsub -Ip -q “xxx” -P “xxx” verdi \ (set the queue)
+ incdir +… /… / testbench \ (reserved in the log file)
+ incdir +… /… / testcase (reserved in log file)
-f… /… / duv / filelist.f (reserved filelist in log file)
… /… / testcase / pipe_test_random_item.sv \ (reserved use case in log file)
+ define +
+ define + (Keep the macro definition in the log file)
-sv
save the file, just run the script.
5. Separate the generation and transmission of incentives (sequence problem) After
all incentives are generated, set up an empty queue in the driver and store the item first. Then control the sending conditions, and then only send the stimulus to duv, so as to separate the generation and sending of the stimulus.
The problem brought by the above is that after the incentive is generated, the platform will be closed, and at this time the process of actually sending all the data to duv and output has not been completed. Therefore, under this kind of operation, it is necessary to set a delay after the stimulus is generated to ensure that all data is completely processed before the platform is shut down.
6. Partial function of driver in interface
When verifying the module, in addition to entering valid and data stimuli upstream, the downstream also needs to enter ready. There is output item ~ agent in UVM, but for some simple processing, it can be realized in output interface.
You can define tasks and functions in the interface, using initial, always, and assign statements. The change mode of the ready signal and the corresponding specific operations in different modes are directly defined in the interface. At the same time, simple operations such as 8b10b encoding can also be completed in the interface, such operations are generally completely irrelevant to the item.
7. Verilog +: Usage
[BASE +: WIDTH] stands for [(BASE + WIDTH-1): BASE], BASE is a variable, and WIDTH is a constant.
Example:
[i * P +: P], i = 0, P = 3, [i * P +: P] = [2: 0].
8. Find value
in verdi Enter the value in bus value, select the signal, and search directly.
It should be noted that the value must be all values, and it does not support searching some values.
