1. Definition of
big endian big endian: high byte first, low byte first;
little endian: high byte first, low byte first;
example: there is a wdata = 0hc2d3_e47f, addr = 0h4000,
The high bit of the data is c2, the low bit is 7f, the high bit of the address is 04, and the low bit is 01.
When using big-endian:
4001 -c2, 4002-d3, 4003-e4, 4004-7f;
when using little-endian:
4001-7f, 4002-e4, 4003-d3, 4004-c2;
usually Internet protocol uses big In end-end mode, the x86 system uses little-endian mode. When data is exchanged between the local and the network, big-endian conversion is required.
2. Verilog realizes big and small end conversion
module top_module
(
input [31:0] in,
output [31:0] out
);
assign out[31:24] =in[ 7: 0];
assign out[23:16] =in[15: 8];
assign out[15: 8] =in[23:16];
assign out[ 7: 0] =in[31:24];
assign out = {in[7-:8],in[15-:8],in[23-:8],in[31-:8]};
endmodule
In practical applications, the first thing to consider for big-endian conversion is data width, 32/64/128/256; secondly, for the axi protocol, the corresponding strb signals need to be converted at the same time; finally, if you consider modularity, you need to define different Branches such as no-endian conversion operations, full conversion operations, or 16-bit conversion operations, and write-read channels.
The above code is a simple 32-bit data width full conversion operation. For axi, such as
data_out = {data_in [7-: 8], data_in [15-: 8], data_in [23-: 8], data_in [31- : 8]};
strb_out = {strb_in [0], strb_in [1], strb_in [2], strb_in [3]};
3. Application in
axi Example: data bus uses big endian, wdata = 0hc2d3_e47f, addr = 0h4001;
module is determined by endian signal, when endian = 1'b0, big endian is used; when endian = 1'b1, small endian is used In
special cases, it is assumed that only the first 6 bits of the 32-bit address are valid, and the high-order address is not allocated and is invalid.
When endian = 1'b0:
axsize = 2, 32-bit effective
wdata_bus = 0hc2d3_e47f
wdata_module = 0hc2d3_e47f (lower 8 bits 0111_1111, the first 6 bits are valid)
actual lower 8-bit stored data 0011_1111
rdata = 0h0000_003f
When endian = 1'b1:
axsize = 2, 32-bit effective
wdata_bus = 0hc2d3_e47f
wdata_module = 0h7fe4_d3c2 (lower 8 bits 1100_0010, the first 6 bits are valid)
actual lower 8-bit stored data 0000_0010
rdata = 0h0000_0002
To achieve the size of the end, you can use reg to control the endian to achieve the conversion, and in special cases, you can directly force the conversion.
In practical application
