Concurrent programming - reordering
When executing the program, in order to improve performance, often have compiler and processor instructions do reordering.
(1) compiler optimizations reordering .
Compiler does not change the semantics of the premise of single-threaded programs, can rearrange the order of execution of the statement
(2) ILP reordering .
Modern processor instruction level parallelism techniques to overlap a plurality of instructions executed. If no data dependency exists, the processor may change the sequence of machine instructions corresponding to the statement
(3) reordering memory system .
Since the processor using the cache and read / write buffer, which makes the load and store operations seem likely to be executed out of order
reordering may result in a multithreaded program memory visibility problems. Ban specific types of compilers and processors reordering provide visibility to ensure consistent memory programmer.
For the compiler to compile JMM's attention sorting rules prohibit a particular type of compiler thinks highly of the sort (not all compilers have discouraged the sort prohibited).
For reordering processor, a processor JMM reordering rules claim Java compiler generates instruction sequence again, the particular type of inserted memory barrier instruction to prohibit a particular type of processor memory barrier instruction by reordering.
Memory barrier
| Barrier type | Instruction type | Explanation |
|---|---|---|
| LoadLoad Barriers | Load1;LoadLoad;Load2 | Load1 ensure data Load2 loaded prior to all subsequent load instruction load |
| StoreStore Barriers | Store1;StoreStore;Store2 | Data storage to ensure Store1 visible to other processors (refresh memory) prior to Store2 and all subsequent store instruction |
| LoadStore Barriers | Load1;LoadStore;Store2 | Load1 salted Store2 ensure data loading and storing all subsequent instructions are flushed to the memory |
| StoreLoad Barriers | Store1; Large Load; Load2 | Store1 ensure data becomes visible (refer to refresh memory) is first loaded in Load2 and all subsequent load instruction to other processors. All memory access instructions (load and store instructions) StoreLoad Barriers will after the barrier before completion, before the implementation of the memory access instruction after the barrier |
StoreLoad Barriers is a "versatile" barriers, it also has the effect of three other barrier. Most modern multi-processor support for the barrier. Implementation of the barrier overhead will be very expensive, because the current processor typically want to write all the data in the buffer to refresh memory (Buffer Fully Flush)
