SOC Scan Synthesis practice (analysis scan chain of the scan chain)

Scan Synthesis practice

1. Positive and negative edge clock edge sequence
   is generally selected following the second, negative along the front edge after n
   
   Analysis Methods:
   Shift in angle:
   
   Syngenta trailing edge of a negative result, at the time of transmission 01, the third n You will get a value along the front edge of the negative. Resulting in a negative and a positive edge along the Federation to adopt the same values.
   shift out angle:
   
   the merits of two structures:
   the case of using the first positive negative: in the case of shift in the, will appear a period of two registers appear as values ;
   to shift out of the case, there will be a second registered negative values appear lost the case , no way to shift out.

So using the first negative clock edge after the positive edge of the structure
to follow the rules: Finally, the capture value of the cell on the frontTo ensure that no one value caputre front.

2. Multiple clock designs
   for the following four cell, whether it is simple before and after connection? (See below)
   
   Clock time of arrival of each register is not the same, will lead to a different time before and after.
   Particular clock edge (clock tree) between clk1 and CLK2:
   
   third second value always capture register (problem relates to clock)
   a first: after clk1, clk2 front (uesful skew)

The first: clk1 first, after clk2 (not used)
will capture new value in advance, leading to the loss of value.

Solution:
For the following cases, can not be simply connected strings

second increase Lock up Cell (LATCH) (anti clock edge), the value corresponding to the falling edge corresponds to a preceding value clk capture later, and to improve The second clock as a first relationship (half CLK)Sacrifice in exchange for setup hold time(Hold more difficult to meet)

3. Related siganl SCAN
   
   Scan the MODE When the test is always 1
   Scan can enable change
   scan input / scan output

4. Design rules - clock
   check cell whether on chain link, if you can not change the design

Add test mode, add MUX, mode = 0 in function mode mode = 1, the chain is in the chain
are two ways this design: RTL changes (mainstream); tools, auto repair

4. Design rules - Reset (set / reset)
   
   after the change results:
   

5. Clock gating cell
   main purpose: to save Power
   
   E: Logic controlled by the function
   TE: the Test the MODE