Mention gas! Ali flathead brother three papers selected ISCA

Author | Ma Chao

Zebian | Hu Weiwei

Exhibition | CSDN (CSDNnew)

Recently, top academic conference ISCA2020 structure of a computer system released the results of selected papers (http://iscaconf.org/isca2020), flat head brother Ali semiconductor companies have selected three papers, setting a record domestic chip companies.

Xuantie 910 papers on which the processor, it is of great significance, not only indicates that China will break through chip instruction set bastion of intellectual property rights by RISC-V, it is completely independent of academic achievement first elected to the ISCA. Earlier in the chip industry at the top of this ISCA, Chinese enterprises papers have not even enrolled the first author record.

In addition two papers, flat head brother respectively with Google, Microsoft and other IT giants proposed solve the memory wall problem "programmable hardware and software architecture based on near-bank architecture," and put forward the industry mainstream hardware performance MLPerf reasoning test platform benchmark.

Top acquaintance will ISCA

ISCA (International Symposium on Computer Architecture) is one of the most authoritative meeting the field of computer architecture, where chips have been ISCA strengths, conference papers selected threshold is very high, very strict assessment criteria, such as this year a total of 421 Paper Submission and finally only 77 were selected, receiving a rate of less than one-fifth. But such a strict inclusion criteria, but also created a top level ISCA, the Conference papers often become an important benchmark development of the industry, including Google, Intel, Nvidia, AMD and other companies published in the ISCA number of research results have become the chip industry benchmark, the number of ISCA selected papers become an important indicator of corporate R & D capabilities of the chip on the processor architecture.

RISC-V: Escape the starting point of the chip instruction set

I have been very concerned about the domestic chip area of development, and development on the road of China's own chip industry, in addition to lithography equipment crossed the road this threshold, the instruction set chip issues also must be resolved.

Popular talk-chip instruction set, somewhat similar to the grammar rules of each programming language, such as Java and C language syntax is completely different types, and in the instruction set, has always had CISC and RISC two styles of wrestling, which CISC instruction set computer means rich, with special instructions to perform specific functions. Therefore, the higher the efficiency of special tasks. The RISC is a reduced instruction set, mainly trying to improve the efficiency of those commonly used instructions for commonly used functions, is accomplished by a combination of instruction. CISC and RISC have advantages and disadvantages, no single style can dominate the political arena.

However, different style open other areas of IT, in chips, the widest range of applications for licensing X86 substantially, while ARM is not only award costs high, but also frequently broke the news of the outage. For example, last year, there are rumors that the UK Acorn Co., Ltd. Huawei and other domestic companies will not authorize Arm v9, although company officials later claimed that ARM will continue to cooperate with Huawei, but such risks and uncertainties, really made we worried about the direction of domestic chip companies.

The RISC-V is precisely a fully open source instruction set, but the key is that it uses a very liberal BSD license, the user is completely free to use for free, but also allowed to add their own instruction set to expand without having to open source to achieve the development of differentiation.

RISC-V is based on reduced instruction set computing open instruction (RISC) established the principle set architecture (ISA), where V represents the Roman numeral 5 represents the fifth generation of RISC instruction set. And each generation of RISC processors are in fact by Professor David A. Patterson at the University of California at Berkeley Laboratory. RISC-V Foundation initiated and established in 2015, which has more than 150 enterprises or units to join, including Google, Ali, Huawei Technologies, NVIDIA, Qualcomm, MIT, Princeton, the University of Dayton, the institute calculated and so on. Recently, spokesman for the Foundation's Mark Sinclair officially confirmed, RISC-V Foundation has completed registration in Switzerland, is currently considering the Foundation moved to neutral Switzerland, to ensure that the university outside the United States, the government and the company are not subject to political influence the use of open source RISC-V. RISC-V can be said that we are a great way to break the chip industry.

From a technical point of view the main features of RISC-V are as follows:

Simple structure: RISC-V RISC architecture to uphold the supremacy of the compact design. I remember ten years ago I was still embedded field work, that time ARM9-based 24x0 series chip has just come out, but its large and complex manuals steep learning curve it, it is still painful.

Like commercial chip ARM architecture, the architecture of the need to maintain backward compatibility, not only retain many commonly used commands, resulting in serious redundancy whole set of instructions, can be said to have gradually become ARM RISC wearing a vest CISC processors. However, in this regard RISC-V is no historical baggage, which is based instruction set only 40 pieces, plus other modular expansion instruction not to 100, just more than 100 pages of official documents.

Easy to transplant: Modern operating systems have done a separate privileged instructions and user-level instruction, privileged instructions can only be invoked in the operating system, and user-level instruction in user mode can be invoked to protect the stability of the operating system. RISC-V provides a privileged instruction and a user-level instructions, while providing detailed RISC-V privileged instruction codes and RISC-V user-level instruction specification information, so that developers can be very easily ported Linux and Unix systems to RISC -V platform.

Modular design: RISC-V can support in a modular way of organizing the chip, the user flexibility to choose different combinations of modules, to achieve their own customized equipment required, such as for low-power embedded in a small area of the scene, the user can choose RV32IC combined instruction set, only the machine mode (machine mode); high-performance applications and the operating system can be selected such scenarios RV32IMFDC instruction set using machine mode (mode machine) and user mode (user mode) modes.

Of course, RISC-V disadvantages are also obvious, such as RISC-V, although complete and open source compilers, development tools and IDE, but commercial and ARM compiler and IDE comparison, is still not perfect. And the history of RISC-V is too short, in fact, the whole industry is still relatively lacking experience in the design RISC-V chip.

Darksteel 910: Surface powerful RISC-V chip

Ali flathead brother always give in progress chips made us a surprise, such as the General Assembly came to power in 2019 Wuzhen no sword 100 on heavy chip platform open source; its AI chip count Han Guang force equivalent to 10 800 GPU, reasoning performance to 78563 IPS, EER 500 IPS / W, compared to traditional GPU calculation power, cost increase of 100%. And based on RISC-V Xuantie 910 processor with 16 cores, 12nm process, clocked at 2.5GHZ, and the industry's first multi-transmitter out of order memory access technology into RISC-V, the performance also will be increased dramatically by 40%.

This time, selected ISCA paper, a comprehensive exposition of the design method Xuantie 910. Darksteel 910 flat head brother's first product, which is currently the industry's highest performance RISC-V processor. 910 Xuantie paper discusses the multiple transmit memory access out of order, and an adaptive hybrid branch processing, multi-channel, multi-mode implementation details of data prefetching techniques. It can be said Xuantie 910 completely broke before the performance limits of RISC-V, to meet the needs of artificial intelligence, network communications, autopilot and other high-performance scene.

Domestic chip industry usher in spring

The nature of the contest between the major powers is on science and technology contest, contest of intellectual property rights, and our high-tech industry wants to self-development, to avoid Western countries stuck his neck, it is necessary to find a breakthrough point, and precisely what we bend Xuantie 910 overtaking benchmark. As we have said before, the selected papers ISCA General Assembly, often industry leader, Ali flathead brother The three selected papers, marking its ability to innovate on the chip reached the international advanced level, we believe that the chip industry is about to usher spring.